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Altera DE1-SoC - User Manual

Altera DE1-SoC
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DE1-SoC User Manual
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www.terasic.com
March 14, 2014
Downloaded from Arrow.com.

Table of Contents

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Summary

DE1-SoC Development Kit

DE1-SoC Development Kit Package Contents

Lists all items included in the DE1-SoC Development Kit package for user convenience.

DE1-SoC System CD Contents

Details the documents and supporting materials available on the DE1-SoC System CD.

Obtaining Support for DE1-SoC

Provides contact information for technical assistance from Altera and Terasic.

Introduction to the DE1-SoC Board

DE1-SoC Board Layout and Components

Identifies key connectors and components on the DE1-SoC development board.

DE1-SoC Board Architecture Overview

Presents a block diagram illustrating the DE1-SoC board's system architecture.

Using the DE1-SoC Board

Configuring FPGA Mode Settings

Explains how to set the FPGA configuration mode using DIP switches.

Configuring the Cyclone V SoC FPGA

Details the JTAG and Active Serial (AS) programming methods for the FPGA.

DE1-SoC Board Status and Reset Features

Describes onboard LEDs for status indication and HPS reset buttons.

DE1-SoC Clock Distribution

Details the clock signals and their distribution on the DE1-SoC board.

FPGA Peripheral Connections

Describes interfaces connecting peripherals to the FPGA for user logic control.

User Input;Output Devices (Buttons, Switches, LEDs)

Explains the functionality of user push-buttons, slide switches, and LEDs.

DE1-SoC 7-segment Displays

Details the six 7-segment displays and their FPGA pin assignments.

DE1-SoC GPIO Expansion Headers

Describes the 2x20 pin expansion headers for connecting daughter cards.

DE1-SoC 24-bit Audio CODEC

Details the WM8731 audio codec for audio input and output.

DE1-SoC I2 C Multiplexer Functionality

Explains the I2C multiplexer used for accessing I2C devices.

DE1-SoC VGA Output Interface

Describes the VGA output connector and its timing specifications.

DE1-SoC TV Decoder (ADV7180)

Details the ADV7180 TV decoder for video signal input and processing.

IR Receiver and Emitter Components

Explains the infrared receiver module and emitter LED for remote control.

DE1-SoC SDRAM Memory Interface

Details the 64MB SDRAM chip and its connections to the FPGA.

DE1-SoC PS;2 Interface

Describes the PS/2 serial port for keyboard and mouse connectivity.

DE1-SoC ADC and 2 x5 Header

Details the 8-channel Analog-to-Digital Converter and its header.

HPS Peripheral Connections

Describes interfaces connected to the Hard Processor System (HPS).

HPS User Input;Output Devices

Explains HPS-specific user interface elements like buttons and LEDs.

DE1-SoC Gigabit Ethernet Interface

Details the Gigabit Ethernet PHY and its pin assignment.

DE1-SoC UART Interface

Describes the UART interface for serial communication via USB.

DE1-SoC HPS DDR3 Memory

Details the 1GB DDR3 SDRAM connected to the HPS.

DE1-SoC Micro SD Card Socket

Describes the Micro SD card socket for storage and boot options.

DE1-SoC 2-Port USB Host

Details the USB 2.0 host ports and associated controller.

DE1-SoC G-sensor (ADXL345)

Explains the ADXL345 accelerometer and its I2C/SPI interfaces.

DE1-SoC LTC Connector Details

Describes the 14-pin LTC connector for daughter card communication.

DE1-SoC System Builder

Introduction to DE1-SoC System Builder

Introduces the Windows-based utility for creating Quartus II projects for DE1-SoC.

DE1-SoC System Builder Design Flow

Outlines the design flow for building Quartus II projects using the System Builder.

Step-by-Step Guide to DE1-SoC System Builder

Provides detailed procedures for installing and using the DE1-SoC System Builder utility.

Examples for FPGA

DE1-SoC Factory Configuration Demonstration

Demonstrates the default board configuration and its features.

Audio Recording and Playing Example

Shows how to implement audio recording and playback using the CODEC.

Karaoke Machine Demonstration

Explains how to set up a Karaoke machine using audio ports and CODEC.

SDRAM Test with Nios II

Illustrates testing SDRAM access and performance using Nios II.

SDRAM Test in Verilog HDL

Demonstrates SDRAM testing using Verilog HDL.

TV Box Demonstration Setup

Details setting up the DE1-SoC as a TV box using video components.

PS;2 Mouse Communication Demonstration

Demonstrates bi-directional communication with a PS/2 mouse.

IR Emitter LED and Receiver Demonstration

Explains using the IR emitter LED and receiver for infrared communication.

ADC Reading Demonstration

Illustrates evaluating the performance of the 8-channel A/D converter.

Examples for HPS SoC

Developing a First HPS Program

Guides on developing and building a basic HPS program using Altera SoC EDS.

Controlling HPS Users LED and KEY

Shows how to control HPS LEDs and keys via GPIO registers.

Controlling G-sensor via I2 C

Demonstrates controlling the G-sensor by accessing its registers via I2C.

Testing the I2 C Multiplexer for HPS Access

Explains switching the I2C multiplexer to allow HPS to access I2C buses.

Examples for HPS SoC and FPGA Interaction

HPS Controlling FPGA LED and HEX

Demonstrates HPS controlling FPGA LEDs and HEX displays through the bridge.

DE1-SoC Control Panel GUI Example

Shows a comprehensive example implementing a GUI to control board peripherals.

Programming the EPCQ Device

Preparing for EPCQ Device Programming

Sets the FPGA to AS x4 mode required for using the quad Flash configuration device.

Converting SOF to JIC File for EPCQ

Details the steps to convert a .sof file to a .jic file using Quartus II Programmer.

Programming the EPCQ Device with JIC File

Explains how to program the EPCQ device using the generated .jic file.

Erasing the EPCQ Device Contents

Describes the procedure to erase existing files from the EPCQ device.

Nios II Booting from EPCQ Device Issue

Notes a known problem regarding Nios II booting from the EPCQ device in Quartus II.

Appendix

DE1-SoC Manual Revision History

Lists the version history and changes made to the DE1-SoC User Manual.

Altera DE1-SoC Specifications

General IconGeneral
ArchitectureARM Cortex-A9
HPS Clock Speed800 MHz
FPGA Logic Elements85K
SD Card SlotYes
Ethernet10/100/1000 Mbps
HDMIYes
Switches4
Push-buttons4
Clock Input50 MHz
Video OutputHDMI
SDRAM1 GByte
USBUSB 2.0
Audio24-bit CODEC
ADC12-bit
Expansion HeadersTwo 40-pin headers

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