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Altera DE1-SoC - DE1-SoC UART Interface

Altera DE1-SoC
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DE1-SoC User Manual
45
www.terasic.com
March 14, 2014
Table 3-24 Pin Assignment of Gigabit Ethernet PHY
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_ENET_TX_EN
PIN_A20
GMII and MII transmit enable
3.3V
HPS_ENET_TX_DATA[0]
PIN_F20
MII transmit data[0]
3.3V
HPS_ENET_TX_DATA[1]
PIN_J19
MII transmit data[1]
3.3V
HPS_ENET_TX_DATA[2]
PIN_F21
MII transmit data[2]
3.3V
HPS_ENET_TX_DATA[3]
PIN_F19
MII transmit data[3]
3.3V
HPS_ENET_RX_DV
PIN_K17
GMII and MII receive data valid
3.3V
HPS_ENET_RX_DATA[0]
PIN_A21
GMII and MII receive data[0]
3.3V
HPS_ENET_RX_DATA[1]
PIN_B20
GMII and MII receive data[1]
3.3V
HPS_ENET_RX_DATA[2]
PIN_B18
GMII and MII receive data[2]
3.3V
HPS_ENET_RX_DATA[3]
PIN_D21
GMII and MII receive data[3]
3.3V
HPS_ENET_RX_CLK
PIN_G20
GMII and MII receive clock
3.3V
HPS_ENET_RESET_N
PIN_E18
Hardware Reset Signal
3.3V
HPS_ENET_MDIO
PIN_E21
Management Data
3.3V
HPS_ENET_MDC
PIN_B21
Management Data Clock Reference
3.3V
HPS_ENET_INT_N
PIN_C19
Interrupt Open Drain Output
3.3V
HPS_ENET_GTX_CLK
PIN_H19
GMII Transmit Clock
3.3V
There are two LEDs, green LED (LEDG) and yellow LED (LEDY), which represent the status of
Ethernet PHY (KSZ9021RNI). The LED control signals are connected to the LEDs on the RJ45
connector. The state and definition of LEDG and LEDY are listed in Table 3-25. For instance, the
connection from board to Gigabit Ethernet is established once the LEDG lights on.
Table 3-25 State and Definition of LED Mode Pins
LED (State)
LED (Definition)
Link /Activity
LEDG
LEDY
LEDG
LEDY
H
H
OFF
OFF
Link off
L
H
ON
OFF
1000 Link / No Activity
Toggle
H
Blinking
OFF
1000 Link / Activity (RX, TX)
H
L
OFF
ON
100 Link / No Activity
H
Toggle
OFF
Blinking
100 Link / Activity (RX, TX)
L
L
ON
ON
10 Link/ No Activity
Toggle
Toggle
Blinking
Blinking
10 Link / Activity (RX, TX)
3
3
.
.
7
7
.
.
3
3
U
U
A
A
R
R
T
T
The board has one UART interface connected for communication with the HPS. This interface
doesn’t support HW flow control signals. The physical interface is implemented by UART-USB
onboard bridge from a FT232R chip to the host with an USB Mini-B connector. More information
about the chip is available on the manufacturers website, or in the directory \Datasheets\UART TO
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