Altera DE1-SoC - SDRAM Test in Verilog HDL

DE1-SoC User Manual
69
www.terasic.com
March 14, 2014
Figure 5-7 Display of progress and result for the SDRAM test in Nios II
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DE1-SoC system CD offers another SDRAM test with its test code written in Verilog HDL. The
memory size of the SDRAM bank tested is still 64MB.
 Function Block Diagram
Figure 5-8 shows the function block diagram of this demonstration. The SDRAM controller uses 50
MHz as a reference clock and generates 100 MHz as the memory clock.
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