Altera DE1-SoC - SDRAM Test with Nios II

DE1-SoC User Manual
66
www.terasic.com
March 14, 2014
Figure 5-5 Setup for the Karaoke machine
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There are many applications use SDRAM as a temporary storage. Both hardware and software
designs are provided to illustrate how to perform memory access in Qsys in this demonstration. It
also shows how Altera’s SDRAM controller IP accesses SDRAM and how the Nios II processor
reads and writes the SDRAM for hardware verification. The SDRAM controller handles complex
aspects of accessing SDRAM such as initializing the memory device, managing SDRAM banks,
and keeping the devices refreshed at certain interval.
 System Block Diagram
Figure 5-6 shows the system block diagram of this demonstration. The system requires a 50 MHz
clock input from the board. The SDRAM controller is configured as a 64MB controller. The
working frequency of the SDRAM controller is 100MHz, and the Nios II program is running on the
on-chip memory.
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