Altera DE1-SoC - DE1-SoC GPIO Expansion Headers

DE1-SoC User Manual
28
www.terasic.com
March 14, 2014
3.6.3 2x20 GPIO Expansion Headers
The board has two 40-pin expansion headers. Each header has 36 user pins connected directly to the
Cyclone V SoC FPGA. It also comes with DC +5V (VCC5), DC +3.3V (VCC3P3), and two GND
pins. The maximum power consumption allowed for a daughter card connected to one or two GPIO
ports is shown in Table 3-10.
Table 3-10 Voltage and Max. Current Limit of Expansion Header(s)
Supplied Voltage
Max. Current Limit
5V
1A
3.3V
1.5A
Each pin on the expansion headers is connected to two diodes and a resistor for protection against
high or low voltage level. Figure 3-18 shows the protection circuitry applied to all 2x36 data pins.
Table 3-11 shows the pin assignment of two GPIO headers.
Figure 3-18 Connections between the GPIO header and Cyclone V SoC FPGA
Table 3-11 Pin Assignment of Expansion Headers
Signal Name
FPGA Pin No.
Description
I/O Standard
GPIO_0[0]
PIN_AC18
GPIO Connection 0[0]
3.3V
GPIO_0 [1]
PIN_Y17
GPIO Connection 0[1]
3.3V
GPIO_0 [2]
PIN_AD17
GPIO Connection 0[2]
3.3V
GPIO_0 [3]
PIN_Y18
GPIO Connection 0[3]
3.3V
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