Altera DE1-SoC - DE1-SoC I2 C Multiplexer Functionality

DE1-SoC User Manual
31
www.terasic.com
March 14, 2014
Figure 3-19 Connections between the FPGA and audio CODEC
Table 3-12 Pin Assignment of Audio CODEC
Signal Name
FPGA Pin No.
Description
I/O Standard
AUD_ADCLRCK
PIN_K8
Audio CODEC ADC LR Clock
3.3V
AUD_ADCDAT
PIN_K7
Audio CODEC ADC Data
3.3V
AUD_DACLRCK
PIN_H8
Audio CODEC DAC LR Clock
3.3V
AUD_DACDAT
PIN_J7
Audio CODEC DAC Data
3.3V
AUD_XCK
PIN_G7
Audio CODEC Chip Clock
3.3V
AUD_BCLK
PIN_H7
Audio CODEC Bit-stream Clock
3.3V
I2C_SCLK
PIN_J12 or PIN_E23
I2C Clock
3.3V
I2C_SDAT
PIN_K12 or PIN_C24
I2C Data
3.3V
3.6.5 I2C Multiplexer
The DE1-SoC board implements an I2C multiplexer for HPS to access the I2C bus originally
owned by FPGA. Figure 3-20 shows the connection of I2C multiplexer to the FPGA and HPS. HPS
can access Audio CODEC and TV Decoder if and only if the HPS_I2C_CONTROL signal is set to
high. The pin assignment of I2C bus is listed in Table 3-13 .
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.