Altera DE1-SoC - FPGA Peripheral Connections

DE1-SoC User Manual
22
www.terasic.com
March 14, 2014
Figure 3-12 Block diagram of the clock distribution on DE1-SoC
Table 3-5 Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
CLOCK_50
PIN_AF14
50 MHz clock input
3.3V
CLOCK2_50
PIN_AA16
50 MHz clock input
3.3V
CLOCK3_50
PIN_Y26
50 MHz clock input
3.3V
CLOCK4_50
PIN_K14
50 MHz clock input
3.3V
HPS_CLOCK1_25
PIN_D25
25 MHz clock input
3.3V
HPS_CLOCK2_25
PIN_F25
25 MHz clock input
3.3V
3
3
.
.
6
6
P
P
e
e
r
r
i
i
p
p
h
h
e
e
r
r
a
a
l
l
s
s
C
C
o
o
n
n
n
n
e
e
c
c
t
t
e
e
d
d
t
t
o
o
t
t
h
h
e
e
F
F
P
P
G
G
A
A
This section describes the interfaces connected to the FPGA. Users can control or monitor different
interfaces with user logic from the FPGA.
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