Altera DE1-SoC - Examples for FPGA; DE1-SoC Factory Configuration Demonstration

DE1-SoC User Manual
60
www.terasic.com
March 14, 2014
Chapter 5
Examples For FPGA
This chapter provides examples of advanced designs implemented by RTL or Qsys on the DE1-SoC
board. These reference designs cover the features of peripherals connected to the FPGA, such as
audio, SDRAM, and IR receiver. All the associated files can be found in the directory
\Demonstrations\FPGA of DE1-SoC System CD.
 Installation of Demonstrations
To install the demonstrations on your computer:
Copy the folder Demonstrations to a local directory of your choice. It is important to make sure the
path to your local directory contains NO space. Otherwise it will lead to error in Nios II. Note
Quartus II v13.0 or later is required for all DE1-SoC demonstrations to support Cyclone V SoC
device.
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The DE1-SoC board has a default configuration bit-stream pre-programmed, which demonstrates
some of the basic features onboard. The setup required for this demonstration and the location of its
files are shown below.
 Demonstration Setup, File Locations, and Instructions
 Project directory: DE1_SoC_Default
 Bitstream used: DE1_SoC_Default.sof or DE1_SoC_Default.jic
 Power on the DE1-SoC board with the USB cable connected to the USB-Blaster II
port. If necessary (that is, if the default factory configuration is not currently stored in
the EPCQ device), download the bit stream to the board via JTAG interface.
 You should now be able to observe the 7-segment displays are showing a sequence of
characters, and the red LEDs are blinking.
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