Altera DE1-SoC - Configuring the Cyclone V SoC FPGA

DE1-SoC User Manual
13
www.terasic.com
March 14, 2014
Table 3-1 FPGA Configuration Mode Switch (SW10)
Board Reference
Signal Name
Description
Default
SW10.1
MSEL0
Use these pins to set the FPGA
Configuration scheme
ON (“0”)
SW10.2
MSEL1
OFF (“1”)
SW10.3
MSEL2
ON (“0”)
SW10.4
MSEL3
ON (“0”)
SW10.5
MSEL4
OFF (“1”)
SW10.6
N/A
N/A
N/A
Figure 3-1 shows MSEL[4:0] setting of AS mode, which is also the default setting on DE1-SoC.
When the board is powered on, the FPGA is configured from EPCQ, which is pre-programmed with
the default code. If developers wish to reconfigure FPGA from an application software running on
Linux, the MSEL[4:0] needs to be set to “01010” before the programming process begins. If
developers using the "Linux Console with frame buffer" or "Linux LXDE Desktop" SD Card image,
the MSEL[4:0] needs to be set to “00000” before the board is powered on.
Table 3-2 MSEL Pin Settings for FPGA Configure of DE1-SoC
MSEL[4:0]
Configure Scheme
Description
10010
AS
FPGA configured from EPCQ (default)
01010
FPPx32
FPGA configured from HPS software: Linux
00000
FPPx16
FPGA configured from HPS software: U-Boot, with
image stored on the SD card, like LXDE Desktop or
console Linux with frame buffer edition.
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There are two types of programming method supported by DE1-SoC:
1. JTAG programming: It is named after the IEEE standards Joint Test Action Group.
The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA. The FPGA will
retain its current status as long as the power keeps applying to the board; the configuration
information will be lost when the power is off.
2. AS programming: The other programming method is Active Serial configuration.
The configuration bit stream is downloaded into the quad serial configuration device (EPCQ256),
which provides non-volatile storage for the bit stream. The information is retained within EPCQ256
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