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Altera Cyclone V SoC - User Manual

Altera Cyclone V SoC
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101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-01135-1.0
User Guide
Cyclone V SoC Development Kit
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Cyclone V SoC Development Kit User Guide

Table of Contents

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Summary

1. About This Kit

Kit Features

Describes the kit contents and capabilities.

Hardware

Lists the hardware components included in the kit.

Software

Describes the software available for the kit.

Quartus II Web Edition Software

Information on obtaining and comparing Quartus II editions.

Cyclone V SoC Development Kit Installer

Details on the license-free installer for the kit.

2. Getting Started

Before You Begin

Checks kit contents and inspects boards before proceeding.

Inspect the Boards

Steps to inspect boards for damage and intact components.

References

Links to related documents and Altera website resources.

3. Software Installation

Installing the Quartus II Web Edition Software

Steps to install the Quartus II Web Edition Software.

Licensing Considerations

Details on the license-free nature of Quartus II Web Edition.

Installing the Altera SoC Embedded Development Suite (EDS)

Information on installing the comprehensive embedded software tool suite.

Installing the Development Kit

Instructions for downloading and installing the Cyclone V SoC Development Kit.

Installing the USB-Blaster II Driver

Guide to installing the necessary driver for host computer communication.

4. Development Board Setup

Setting Up the Board

Steps to prepare and power up the Cyclone V SoC development board.

Factory Default Switch and Jumper Settings

Shows factory settings for switches and jumpers for proper function.

Restoring the MAX V CPLD to the Factory Settings

Procedure to restore original factory contents to the MAX V CPLD.

5. Board Update Portal

Connecting to the Board Update Portal Web Page

Instructions to access the Board Update Portal web page.

6. Board Test System

Preparing the Board

Steps to prepare the board for running the Board Test System.

Running the Board Test System

Instructions to launch and run the BoardTestSystem.exe application.

The System Info Tab

Displays board configuration, registers, MAC addresses, and flash map.

Board Information

Controls that display static information about the board.

JTAG Chain

Shows devices in the JTAG chain and their order.

The GPIO Tab

Allows interaction with user I/O components like LCD, LEDs, and switches.

Character LCD

Controls for displaying text strings on the character LCD.

User DIP Switch

Displays current positions of user DIP switches on the board.

User LEDs

Controls the state of user LEDs, allowing them to be turned on/off.

Push Button Switches

Displays the current state of the board's user push buttons.

The I2 C Tab

Allows reading and writing to the I2C EEPROM on the development board.

EEPROM

Details about the serial I2C EEPROM, including start address and range.

RTC

Information about the Real Time Clock (RTC) functionality.

The DDR3 Tab

Allows reading and writing to the DDR3 memory on the board.

Start

Initiates DDR3 memory transaction performance analysis.

Stop

Terminates DDR3 memory transaction performance analysis.

Performance Indicators

Displays current transaction performance analysis information.

Error Control

Displays data errors detected during analysis and allows error insertion.

Number of Addresses to Write and Read

Determines the number of addresses used in read/write iterations.

The SDI Video Tab

Allows testing of the SDI video interface on the board.

Pattern Generator

Specifies test patterns for output to the monitor.

Intensity

Specifies the color intensity of the transmitted color bar pattern.

SDI Standard

Specifies the video standard used for the SDI video stream.

Clock Source

Specifies the clock used by the SDI PLL to lock onto.

Data Test

Displays SDI interface test information when running in PRBS mode.

The HSMC Tab

Performs loopback tests on XCVR, LVDS, and CMOS ports.

XCRV, LVDS, CMOS

Displays status information for XCRV, LVDS, and CMOS during loopback tests.

The Power Monitor

Measures and reports current power information for the board.

U34 and U26

Shows power rail graphs displaying mA power consumption over time.

Temp on 2978

Displays temperature from the power supply manager.

Total Power

Displays the sum of power rails for groups U34 and U26.

The Clock Control

Application to set programmable oscillators for frequencies between 10 MHz and 810 MHz.

Serial Port Registers

Shows current values from the Si570 registers.

fXTAL

Shows calculated internal fixed-frequency crystal based on serial port registers.

Target Frequency

Allows specifying the clock frequency with high precision.

Configuring the FPGA Using the Quartus II Programmer

Steps to configure the FPGA with a specific .sof file using Quartus II Programmer.

A. Programming Flash Memory

CFI Flash Memory

Describes preprogrammed contents of the CFI flash memory.

CFI Flash Memory Map

Details the default memory contents of the 512-Mb CFI flash device.

Converting.sof Files to a.pof

Procedure to generate a flash programming file from .sof files.

Restoring the CFI Flash Device to the Factory Defaults

Steps to program the factory image back to the flash device.

QSFI Flash Memory

Information on programming QSPI flash using the Quartus II programmer.

Programming QSPI Flash using the Quartus II Programmer

Instructions to program QSPI flash using the quartus_hps.exe tool.

SDI Card Memory

Details about the SD card as the default HPS boot source.

The SD Card Default HPS Boot Source

Explains how the SD card is used as the default boot source for HPS.

Additional Information

Document Revision History

Provides the revision history for the user guide document.

How to Contact Altera

Information on how to contact Altera for support and literature.

Typographic Conventions

Explains the typographic conventions used throughout the document.

Altera Cyclone V SoC Specifications

General IconGeneral
BrandAltera
ModelCyclone V SoC
CategoryMicrocontrollers
LanguageEnglish

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