Altera DE1-SoC - Block Diagram of the DE1-Soc Board

DE1-SoC User Manual
8
www.terasic.com
March 14, 2014
The following hardware is provided on the board:
 FPGA
 Altera Cyclone® V SE 5CSEMA5F31C6N device
 Altera serial configuration device – EPCQ256
 USB-Blaster II onboard for programming; JTAG Mode
 64MB SDRAM (16-bit data bus)
 4 push-buttons
 10 slide switches
 10 red user LEDs
 Six 7-segment displays
 Four 50MHz clock sources from the clock generator
 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks
 VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
 TV decoder (NTSC/PAL/SECAM) and TV-in connector
 PS/2 mouse/keyboard connector
 IR receiver and IR emitter
 Two 40-pin expansion header with diode protection
 A/D converter, 4-pin SPI interface with FPGA
 HPS (Hard Processor System)
 800MHz Dual-core ARM Cortex-A9 MPCore processor
 1GB DDR3 SDRAM (32-bit data bus)
 1 Gigabit Ethernet PHY with RJ45 connector
 2-port USB Host, normal Type-A USB connector
 Micro SD card socket
 Accelerometer (I2C interface + interrupt)
 UART to USB, USB Mini-B connector
 Warm reset button and cold reset button
 One user button and one user LED
 LTC 2x7 expansion header
2
2
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2
B
B
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l
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o
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c
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k
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D
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r
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C
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d
Figure 2-3 is the block diagram of the board. All the connections are established through the
Cyclone V SoC FPGA device to provide maximum flexibility for users. Users can configure the
FPGA to implement any system design.
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