Altera DE1-SoC - Page 10

DE1-SoC User Manual
9
www.terasic.com
March 14, 2014
Figure 2-3 Block diagram of DE1-SoC
Detailed information about Figure 2-3 are listed below.
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 Cyclone V SoC 5CSEMA5F31 Device
 Dual-core ARM Cortex-A9 (HPS)
 85K programmable logic elements
 4,450 Kbits embedded memory
 6 fractional PLLs
 2 hard memory controllers
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 Quad serial configuration device – EPCQ256 on FPGA
 Onboard USB-Blaster II (normal type B USB connector)
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