Altera DE1-SoC - Step-by-Step Guide to DE1-SoC System Builder

DE1-SoC User Manual
54
www.terasic.com
March 14, 2014
The DE1-SoC System Builder will generate two major files, a top-level design file (.v) and a
Quartus II setting file (.qsf) after users launch the DE1-SoC System Builder and create a new
project according to their design requirements
The top-level design file contains a top-level Verilog HDL wrapper for users to add their own
design/logic. The Quartus II setting file contains information such as FPGA device type, top-level
pin assignment, and the I/O standard for each user-defined I/O pin.
Finally, the Quartus II programmer is used to download .sof file to the development board via JTAG
interface.
Figure 4-1 Design flow of building a project from the beginning to the end
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This section provides the procedures in details on how to use the DE1-SoC System Builder.
 Install and Launch the DE1-SoC System Builder
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