Altera DE1-SoC - DE1-SoC 7-segment Displays

DE1-SoC User Manual
26
www.terasic.com
March 14, 2014
Table 3-8 Pin Assignment of LEDs
Signal Name
FPGA Pin No.
Description
I/O Standard
LEDR[0]
PIN_V16
LED [0]
3.3V
LEDR[1]
PIN_W16
LED [1]
3.3V
LEDR[2]
PIN_V17
LED [2]
3.3V
LEDR[3]
PIN_V18
LED [3]
3.3V
LEDR[4]
PIN_W17
LED [4]
3.3V
LEDR[5]
PIN_W19
LED [5]
3.3V
LEDR[6]
PIN_Y19
LED [6]
3.3V
LEDR[7]
PIN_W20
LED [7]
3.3V
LEDR[8]
PIN_W21
LED [8]
3.3V
LEDR[9]
PIN_Y21
LED [9]
3.3V
3.6.2 7-segment Displays
The DE1-SoC board has six 7-segment displays. These displays are paired to display numbers in
various sizes. Figure 3-17 shows the connection of seven segments (common anode) to pins on
Cyclone V SoC FPGA. The segment can be turned on or off by applying a low logic level or high
logic level from the FPGA, respectively.
Each segment in a display is indexed from 0 to 6, with corresponding positions given in Figure
3-17. Table 3-9 shows the pin assignment of FPGA to the 7-segment displays.
Figure 3-17 Connections between the 7-segment display HEX0 and the Cyclone V SoC FPGA
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