Altera DE1-SoC - DE1-SoC VGA Output Interface

DE1-SoC User Manual
32
www.terasic.com
March 14, 2014
Figure 3-20 Control mechanism for the I2C multiplexer
Table 3-13 Pin Assignment of I2C Bus
Signal Name
FPGA Pin No.
Description
I/O Standard
FPGA_I2C_SCLK
PIN_J12
FPGA I2C Clock
3.3V
FPGA_I2C_SDAT
PIN_K12
FPGA I2C Data
3.3V
HPS_I2C1_SCLK
PIN_E23
I2C Clock of the first HPS I2C concontroller
3.3V
HPS_I2C1_SDAT
PIN_C24
I2C Data of the first HPS I2C concontroller
3.3V
HPS_I2C2_SCLK
PIN_H23
I2C Clock of the second HPS I2C concontroller
3.3V
HPS_I2C2_SDAT
PIN_A25
I2C Data of the second HPS I2C concontroller
3.3V
3.6.6 VGA
The DE1-SoC board has a 15-pin D-SUB connector populated for VGA output. The VGA
synchronization signals are generated directly from the Cyclone V SoC FPGA, and the Analog
Devices ADV7123 triple 10-bit high-speed video DAC (only the higher 8-bits are used) transforms
signals from digital to analog to represent three fundamental colors (red, green, and blue). It can
support up to SXGA standard (1280*1024) with signals transmitted at 100MHz. Figure 3-21 shows
the signals connected between the FPGA and VGA.
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