Altera DE1-SoC - DE1-SoC HPS DDR3 Memory

DE1-SoC User Manual
46
www.terasic.com
March 14, 2014
USB of DE1-SoC system CD. Figure 3-32 shows the connections between the HPS, FT232R chip,
and the USB Mini-B connector. Table 3-26 lists the pin assignment of UART interface connected to
the HPS.
Figure 3-32 Connections between the HPS and FT232R Chip
Table 3-26 Pin Assignment of UART Interface
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_UART_RX
PIN_B25
HPS UART Receiver
3.3V
HPS_UART_TX
PIN_C25
HPS UART Transmitter
3.3V
HPS_CONV_USB_N
PIN_B15
Reserve
3.3V
3
3
.
.
7
7
.
.
4
4
D
D
D
D
R
R
3
3
M
M
e
e
m
m
o
o
r
r
y
y
The DDR3 devices connected to the HPS are the exact same model as the ones connected to the
FPGA. The capacity is 1GB and the data bandwidth is in 32-bit, comprised of two x16 devices with
a single address/command bus. The signals are connected to the dedicated Hard Memory Controller
for HPS I/O banks and the target speed is 400 MHz. Table 3-27 lists the pin assignment of DDR3
and its description with I/O standard.
Table 3-27 Pin Assignment of DDR3 Memory
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_DDR3_A[0]
PIN_F26
HPS DDR3 Address[0]
SSTL-15 Class I
HPS_DDR3_A[1]
PIN_G30
HPS DDR3 Address[1]
SSTL-15 Class I
HPS_DDR3_A[2]
PIN_F28
HPS DDR3 Address[2]
SSTL-15 Class I
HPS_DDR3_A[3]
PIN_F30
HPS DDR3 Address[3]
SSTL-15 Class I
HPS_DDR3_A[4]
PIN_J25
HPS DDR3 Address[4]
SSTL-15 Class I
HPS_DDR3_A[5]
PIN_J27
HPS DDR3 Address[5]
SSTL-15 Class I
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