Altera DE1-SoC - Page 71

DE1-SoC User Manual
70
www.terasic.com
March 14, 2014
Figure 5-8 Block diagram of the SDRAM test in Verilog
RW_test module writes the entire memory with a test sequence first before comparing the data read
back with the regenerated test sequence, which is same as the data written to the memory. KEY0
triggers test control signals for the SDRAM, and the LEDs will indicate the test result according to
Table 5-3.
 Design Tools
 Quartus II v13.1
 Demonstration Source Code
 Project directory: DE1_SoC_SDRAM_RTL_Test
 Bitstream used: DE1_SoC_SDRAM_RTL_Test.sof
 Demonstration Batch File
Demo batch file folder: \DE1_SoC_SDRAM_RTL_Test\demo_batch
The directory includes the following files:
 Batch file: DE1_SoC_SDRAM_RTL_Test.bat
 FPGA configuration file: DE1_SoC_SDRAM_RTL_Test.sof
 Demonstration Setup
 Quartus II v13.1 must be pre-installed to the host PC.
 Connect the DE1-SoC board (J13) to the host PC with a USB cable and install the
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