Altera DE1-SoC - DE1-SoC Board Status and Reset Features

DE1-SoC User Manual
18
www.terasic.com
March 14, 2014
Figure 3-8 Program .sof file into the FPGA device
 Configure the FPGA in AS Mode
 The DE1-SoC board uses a quad serial configuration device (EPCQ256) to store
configuration data for the Cyclone V SoC FPGA. This configuration data is
automatically loaded from the quad serial configuration device chip into the FPGA
when the board is powered up.
 Users need to use Serial Flash Loader (SFL) to program the quad serial configuration
device via JTAG interface. The FPGA-based SFL is a soft intellectual property (IP)
core within the FPGA that bridge the JTAG and Flash interfaces. The SFL
Megafunction is available in Quartus II. Figure 3-9 shows the programming method
when adopting SFL solution.
 Please refer to Chapter 9: Steps of Programming the Quad Serial Configuration Device
for the basic programming instruction on the serial configuration device.
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