Altera DE1-SoC - DE1-SoC SDRAM Memory Interface

DE1-SoC User Manual
39
www.terasic.com
March 14, 2014
Figure 3-26 Connections between the FPGA and SDRAM
Table 3-20 Pin Assignment of SDRAM
Signal Name
FPGA Pin No.
Description
I/O Standard
DRAM_ADDR[0]
PIN_AK14
SDRAM Address[0]
3.3V
DRAM_ADDR[1]
PIN_AH14
SDRAM Address[1]
3.3V
DRAM_ADDR[2]
PIN_AG15
SDRAM Address[2]
3.3V
DRAM_ADDR[3]
PIN_AE14
SDRAM Address[3]
3.3V
DRAM_ADDR[4]
PIN_AB15
SDRAM Address[4]
3.3V
DRAM_ADDR[5]
PIN_AC14
SDRAM Address[5]
3.3V
DRAM_ADDR[6]
PIN_AD14
SDRAM Address[6]
3.3V
DRAM_ADDR[7]
PIN_AF15
SDRAM Address[7]
3.3V
DRAM_ADDR[8]
PIN_AH15
SDRAM Address[8]
3.3V
DRAM_ADDR[9]
PIN_AG13
SDRAM Address[9]
3.3V
DRAM_ADDR[10]
PIN_AG12
SDRAM Address[10]
3.3V
DRAM_ADDR[11]
PIN_AH13
SDRAM Address[11]
3.3V
DRAM_ADDR[12]
PIN_AJ14
SDRAM Address[12]
3.3V
DRAM_DQ[0]
PIN_AK6
SDRAM Data[0]
3.3V
DRAM_DQ[1]
PIN_AJ7
SDRAM Data[1]
3.3V
DRAM_DQ[2]
PIN_AK7
SDRAM Data[2]
3.3V
DRAM_DQ[3]
PIN_AK8
SDRAM Data[3]
3.3V
DRAM_DQ[4]
PIN_AK9
SDRAM Data[4]
3.3V
DRAM_DQ[5]
PIN_AG10
SDRAM Data[5]
3.3V
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