Altera DE1-SoC - DE1-SoC Board Status and Reset Features

DE1-SOC COMPUTER SYSTEM WITH NIOS II For Quartus II 15.0
CHECK_LEVEL_0: /* interval timer is interrupt level 0 */
andi r22, et, 0b1
beq r22, r0, CHECK_LEVEL_1
call INTERVAL_TIMER_ISR
br END_ISR
CHECK_LEVEL_1: /* pushbutton port is interrupt level 1 */
andi r22, et, 0b10
beq r22, r0, END_ISR /* other interrupt levels are not handled in this code */
call PUSHBUTTON_ISR
END_ISR:
ldw et, 0(sp) /* restore all used register to previous values */
ldw ea, 4(sp)
ldw ra, 8(sp) /* needed if call inst is used */
ldw r22, 12(sp)
addi sp, sp, 16
eret
.end
Figure 17. Reset and exception handler assembly language code (Part b).
.include "key_codes.s" /* includes .equ for KEY0, KEY1, . .. */
.extern PATTERN /* externally defined variables */
.extern KEY_PRESSED
.extern SHIFT_DIR
/********************************************************************************
* Interval timer interrupt service routine
*
* Shifts a PATTERN being displayed on the HEX displays. The shift direction
* is determined by the external variable KEY_PRESSED.
********************************************************************************/
.global INTERVAL_TIMER_ISR
INTERVAL_TIMER_ISR:
subi sp, sp, 40 /* reserve space on the stack */
stw ra, 0(sp) /* save registers */
stw r4, 4(sp)
stw r5, 8(sp)
stw r6, 12(sp)
Figure 18. Interrupt service routine for the interval timer (Part a).
Altera Corporation - University Program
2015
19