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DRAM Timing Control
DRAM Slot
Use this item to view SPD data.
DRAM Timing Control
Use this item to control DRAM timing.
Power Down Enable
Use this item to enable or disable DDR power down mode.
Bank Interleaving
Interleaving allows memory accesses to be spread out over banks on the
same node, or accross nodes, decreasing access contention.
Channel Interleaving
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tions: [Disabled], [Auto]. The default value is [Auto].
DRAM Voltage
APU PCIE Voltage VDDP
SB Voltage
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