Atari 800

NMIST (Non Maskable Interrupt Status)(D40F): This address read the NMI
Status Register (Read by OS NMI code).
D7 D6
0 no interrupt
1 interrupt
D5
Not
Used
D7 This bit identifies an NMI interrupt caused by bit 7 of a
Display List Instruction.
D6 This bit identifies an NMI interrupt caused by the beginning
of vertical blank.
D5 This bit identifies an NMI interrupt caused by the SYSTEM
RESET outton.
NMIRES (NMI Status Register Reset)(D40F): This write address resets
the Non Maskable Interrupt Status Register (NMIST).
Not
Used
(
Written by OS NMI code.)
IRQST (IRQ Interrupt Status)(D20E): This address reads the data from
the IRQ Interrupt Status Register.
D7
0 = Interrupt
1 No Interrupt
D6 D5 D4 D3 D2 D1
DO
D7 0
Break Key Interrupt
D6
0
Other Key Interrupt
D5
0
Se
rial Input Data Ready Interrupt
D4
=
0
Serial Output Data Needed Interrupt
D3 0
Serial Output (Byte) Transmission Finished
Interrupt *
D2
0
Timer 4 Interrupt
D1 0 Timer
2 Interrupt
DO
0 Timer
1 Interrupt
* - NOTE: Used for generation of 2 stop bits. See IRQ description
in section II (no direct reset on bit 3).
III.2