Atari 800

III. HARDWARE REGISTERS
This section lists the hardware registers and Operating System (OS)
shadow
registers.
In the following descriptions, true always refers to a bit whose value
is 1.
A. PAL (D 014)
Not
D3 D2 D1
!Not I
Used !Used
D3
D2 D1
1
1
1
NTSC (US TV)
0 0 0
PAL (European TV)
This byte
can be read by a program to determine
which type of system
the
program is running on.
B. INTERRUPT CONTROL
NMIEN (Non Maskable Interrupt Enable)(D40E): This address writes data
to the NMI interrupt enable bits.
D7 D6
0 disabled (masked)
1
= enabled
Not
Used
D7 Display List Instruction Interrupt Enable. This bit is
cleared by Power Reset, and may be set or cleared by the
processor.
D6 Vertical Blank Interrupt Enable. This bit is cleared by Power
Reset, and may be set or cleared by the processor.
SYSTEM RESET Button Interrupt
This interrupt is always enabled. The SYSTEM RESET button should
not be pressed during power turn on.
(Set to hex 40 by OS IRQ code.)
III.1