Microcontroller
5-114
Clock
The AT89C51/52 Clock must be running during flash writ-
ing. Most boards have clock circuits which will be normally
running while the board is on its fixture with power applied.
If the program contains a feature that disables the clock,
you will need to defeat it for the duration of this test page. If
you use a single-chip fixture to debug your application, you
will need to add a crystal in the single-chip fixture.
AT89C51/52 Pin Name DR2p Signal Name/Node# Notes
P0.0 192 (DR2p 0 - group A) Portwise Bidirectional
P0.1 193 (DR2p 0 - group A)
P0.2 194 (DR2p 0 - group A)
P0.3 195 (DR2p 0 - group A)
P0.4 196 (DR2p 0 - group A)
P0.5 197 (DR2p 0 - group A)
P0.6 198 (DR2p 0 - group A)
P0.7 199 (DR2p 0 - group A)
P1.0 (A0) 224 (DR2p 1 - group A and B) Address counter - 13 bits
P1.1 (A1) 225 (DR2p 1 - group A and B)
P1.2 (A2) 226 (DR2p 1 - group A and B)
P1.3 (A3) 227 (DR2p 1 - group A and B)
P1.4 (A4) 228 (DR2p 1 - group A and B)
P1.5 (A5) 229 (DR2p 1 - group A and B)
P1.6 (A6) 230 (DR2p 1 - group A and B)
P1.7 (A7) 231 (DR2p 1 - group A and B)
P2.0 (A8) 232 (DR2p 1 - group A and B)
P2.1 (A9) 233 (DR2p 1 - group A and B)
P2.2 (A10) 234 (DR2p 1 - group A and B)
P2.3 (A11) 235 (DR2p 1 - group A and B)
P2.4 (A12) 236 (DR2p 1 - group A and B)
P2.6 200 (DR2p 0 - group B) Outputs from DFP to DUT
P2.7 201 (DR2p 0 - group B)
P3.6 202 (DR2p 0 - group B)
P3.7 203 (DR2p 0 - group B)
RST 204 (DR2p 0 - group B)
EA
/V
PP
205 (DR2p 0 - group B)
ALE/PROG 206 (DR2p 0 - group B)
PSEN
207 (DR2p 0 - group B)
P3.4 (RDY/BUSY
) 208 (DR2p 0 - group C) Input from DFP to DUT
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