Atmel AT89C52 - Page 15

t
GLGH
t
AVGL
t
SHGL
t
DVGL
t
GHAX
t
AVQV
t
GHDX
t
EHSH
t
ELQV
t
WC
BUSY
READY
t
GHBL
t
EHQZ
P1.0 - P1.7
P2.0 - P2.4
P3.0
ALE/PROG
PORT 0
LOGIC 1
LOGIC 0
EA/V
PP
P2.7
(ENABLE)
P3.4
(RDY/BSY)
PROGRAMMING
ADDRESS
VERIFICATION
ADDRESS
DATA IN
DATA OUT
Flash Programming and Verification Waveforms - Low Voltage Mode
t
GLGH
t
GHSL
t
AVGL
t
SHGL
t
DVGL
t
GHAX
t
AVQV
t
GHDX
t
EHSH
t
ELQV
t
WC
BUSY
READY
t
GHBL
t
EHQZ
P1.0 - P1.7
P2.0 - P2.4
P3.0
ALE/PROG
PORT 0
LOGIC 1
LOGIC 0
EA/V
PP
V
PP
P2.7
(ENABLE)
P3.4
(RDY/BSY)
PROGRAMMING
ADDRESS
VERIFICATION
ADDRESS
DATA IN
DATA OUT
Flash Programming and Verification Waveforms - High Voltage Mode
AT89C52
15