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7598H–AVR–07/09

ATtiny25/45/85

Figure 13-2. Prescaler for Timer/Counter0

Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 13-1.

13.2.1 General Timer/Counter Control Register – GTCCR

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted.

This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-

ing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by

hardware, and the Timer/Counter start counting.

• Bit 0 – PSR0: Prescaler Reset Timer/Counter0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared

immediately by hardware, except if the TSM bit is set.

PSR10

Clear

clk

I/O

Synchronization

Bit 7 6 5 4 3 2 1 0

TSM

PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR

Read/Write R/W R R R R R R R/W

Initial Value 0 0 0 0 0 0 0 0

Atmel ATtiny85 User Manual

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