BE1-81 Functional Description
3-3
Synchronizer Circuit
This circuit synchronizes the squarewave (representative of the input waveform) with the crystal
reference oscillator to generate a synchronized zero crossing pulse. The zero crossing pulse resets the
system timing. Each time this zero crossing pulse occurs, a new frequency comparison is initiated.
Reference Circuit
This circuit generates a reference signal each 16.667 millisecond (60 hertz nominal system frequency)
or 20.000 ms (50 hertz nominal system frequency) after a synchronized zero crossing pulse. This signal
is generated by counting pulses from the reference oscillator. When the proper count is reached, an
output signal is applied to the period difference circuit.
Period Difference Circuit
This circuit initiates a train of pulses beginning with the occurrence of the reference signal and ending
when the synchronized zero crossing pulse occurs. The time span between these two signals is the
difference in period between the sensing input waveform and the nominal system frequency. Each pulse
in the pulse train represents a one microsecond difference in period.
Period Difference To Frequency Difference Circuit
This circuit converts the pulses received from the period difference circuit to one pulse for each 0.05
hertz difference from the nominal frequency. This is accomplished by a variable scale divider which
compensates for the inverse relationship between period and frequency.
Threshold Setting Comparator
This circuit counts the number of pulses coming from the frequency difference circuit and compares it
with the front panel control setting. When the frequency decreases beyond the difference established by
the front control, an output pulse is applied to the appropriate timing circuit.
Definite Time Delay Circuit (Timing Option E1)
The definite time delay circuit counts the number of consecutive cycles of the underfrequency waveform
after the threshold setting comparator output pulse occurs. When the number of underfrequency cycles
equals the front panel time delay setting, a pulse is generated to the output trip circuit. It is
recommended that the time delay control be set for a minimum of three cycles delay to reduce the
possibility of a trip signal caused by transient-generated underfrequency conditions.
Inverse Time Delay Circuit (Timing Option D1)
The inverse time delay circuit uses the magnitude of the underfrequency condition to determine the time
delay. A set of pulses, representative of the magnitude of the underfrequency condition, is applied to an
RC network to generate an inverse time delay. A front panel dial permits adjustment of the time curve
over the applicable 60 hertz or 50 hertz system range. An LED on the front panel indicates that the relay
pickup setting has been exceeded.
Relay Output
Either normally closed or normally open relay output contacts may be selected. An optional set of
auxiliary relay contacts may be specified when the relay auxiliary output option is selected. The relay
contacts remain in the energized condition as long as the sensed input is below pickup.
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