Bg BG0836 - PLL Control; Main System Clock Control; Figure 12 PLL Block Diagram; Table 10 PLL Control Register

V1.2
BG0836 1/2.7 inch 1080P HD CMOS image sensor
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PLL control
pre-divider
pln_p<5:0>
clkin
PFD
CP
LPF
VCO
vco_fsel_p<1:0>
loop-divider
plm_p<8:0>
pllclk_sel
clkin
fvco
fvco
pln_p+2
plm_p+2
pclk_sel
pclkdiv<2:0>
fpll=fvco
fpll
pclkdiv+2
pixclk
Figure 12 PLL block diagram
The relationship between output Pclk frequency and clkin frequency is :



󰇛
  
󰇜
 

󰇛
  
󰇜
 󰇛  󰇜
Registers corresponding to PLL are listed in Table 10:
Table 10 PLL control register
Register
Addr
Width
Function
PLM
0x00f3
0x00f4
9
PLM data
PLN
0x00f5
6
PLN data
PCLK_CTRL
0x006d
7
Bit[6] Reserved
Bit[5:4] vco_freq_sel
Bit[2:0] pclkdiv
When you adjust vco oscillation frequency, you need to set vco_freq_sel of PLLCTRL_P. Formula
for vco frequency is


 

 󰇛  󰇜 󰇛  󰇜

Setting vco_freq_sel according to the following table.
Table 11 PLL VCO frequency setting up corresponding table
vco_freq_sel<1:0>
vco frequency range
00 B
200M ~ 380M
01 B
230M ~ 460M
10 B
360M ~ 600M
11 B
500M ~ 770M
Main System Clock control
Mclk（Main System Clock）can be chosen as Clkin (external clock ) or the frequency
multiplication of Pclk(Pixel output clock).