Bg BG0836 - Pin Configuration; Figure 2 Pin Configuration; Table 2 Pin Description

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V1.2

BG0836 1/2.7 inch 1080P HD CMOS image sensor

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Pin configuration

VDDA

PCLK

VSS

VDA15

D0/DN

D1/DP0

SDA

VSSD

CLKIN

VSSA

HSYNC

/CKN

VSYNC

/CKP

VDDD

TRIG

SCL

VDDIO

VSSA

VDD15

D11

VSS

VDD15

RSTB

VDD15

D10

VDDA

VSSA

VDDPI

VDD15

VSS

VDDPI

VSSA

VDDA

VSSA

VDDA

VSS

VDD15

VDDA

VSSA

VDDA

Figure 2 Pin configuration shows the pin configuration from top view. Table 2 lists the

pin description.

VDDA

PCLK

VSS

VDA15

D0/DN

D1/DP0

SDA

VSSD

CLKIN

VSSA

HSYNC

/CKN

VSYNC

/CKP

VDDD

TRIG

SCL

VDDIO

VSSA

VDD15

D11

VSS

VDD15

RSTB

VDD15

D10

VDDA

VSSA

VDDPI

VDD15

VSS

VDDPI

VSSA

VDDA

VSSA

VDDA

VSS

VDD15

VDDA

VSSA

VDDA

Figure 2 Pin configuration

Table 2 pin description

(P=Power, G=Ground, D=Digital, A=Analog)

PIN NO

NAME

I/O

TYPE

DESCRIPTION

VDDA

Analog 3.3V power supply

Reference voltage

PCLK

Pixel sync clock

VSS

Digital ground

Main Page

Table of Contents2
Table 1 Key Specification2
PCB Design Guideline5
Package Diagram5
Figure 1 Mechanical Drawing5
Pin Configuration6
Figure 2 Pin Configuration6
Table 2 Pin Description6
Application Circuits8
Figure 3 Recommended Schematic with MIPI Interface8
Power Supply Design9
Figure 4 Recommended Schematic with DVP Interface9
Figure 5 Recommend Power Tree（1.8V IO9
Table 3 Power Supply Requirement（Mipi Mode9
Table 4 Power Supply Requirement（Dvp Mode10
Table 5 IO Level Configuration10
PCB Notice11
Checklist11
Register Slave Interface11
I2C Slave Interface11
Figure 6 Power-Up Sequence11
Figure 7 I2C Write Operation11
Figure 8 I2C Read Operation12
Shadow Register13
Optical Design13
Imaging Direction13
Table 6 BG0836 PID13
Table 7 Shadow Register Update Control13
Mirror Function14
Figure 9 Imaging a Scene14
Figure 10 Mirror Function Schematic14
Table 8 Mirror Control Register14
Adjust the Wide and Frame Rate15
CFA Assignment15
The Calculation of the Clock15
The Definition of the Clock15
Figure 11 Color Filter Arrangements15
Table 9 Clock Definition15
PLL Control16
Main System Clock Control16
Figure 12 PLL Block Diagram16
Table 10 PLL Control Register16
Table 11 PLL VCO Frequency Setting up Corresponding Table16
Adjust the Size17
Adjust the Frame Rate17
Figure 13 Output Waveform and Frame Rate Calculation17
Table 12 Main System Clock Control17
Table 13 Control the Output Format Registers17
Adjust the Exposure and Gain18
Adjust the Exposure18
Table 14 Frame Rate Control Register18
Adjust the Gain19
Table 15 Exposure Control Register19
Table 16 Analog Gain Control Registers19
Table 17 Digital Gain Control Registers19
Adjust the Gain Strategy20
Black Level Calibration20
Table 18 BLC Control Register20
Mipi21
Figure 14 BLC Convergence Signal21
Table 19 Mipi Control Register21
Others22
IO Adjust the Drive Ability22
Pixel Clock Phase Adjustment22
Figure 15 Raw10/Raw12 Data Output Sequence22
Figure 16 Mipi Frame Timing22
Table 20 Adjust the Driving Ability Registers22
Table 21 Adjust Pclk Phase Position22
Fqa23
Revision History24

Bg BG0836 - Pin Configuration; Figure 2 Pin Configuration; Table 2 Pin Description

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