59
IC Diagrams
Functional Block Diagram—Processor Core
ADDR DATA
IOD
ADDR DATA
IOA
ADDR DATA
IOA
SRAM
1M BIT ROM
2M BIT
SRAM
0.5M BIT
BLOCK0 BLOCK1 BLOCK2 BLOCK3
ADDR DATA
IOA
IOP REGISTERS
(MEMORY MAPPED)
I/O PROCESSOR
AND PERIPHERALS
6
JTAG TEST AND EMULATION
32
PM ADDRESS BUS
DM ADDRESS BUS
32
PM DATA BUS
DM DATA BUS
64
64
PX REGISTER
PROCESSING
ELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32-BIT
48-BIT
DAG1
8432
DAG2
8432
CORE PROCESSOR
PROGRAM
SEQUENCER
SRAM
1M BIT ROM
2M BIT
SIGNAL
ROUTING
UNIT
SRAM
0.5M BIT
4 BLOCKS OF ON-CHIP MEMORY
IOD IOA IOD IOD
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
BGA Pin Assignments (Top View)
A
VSS
V
DDINT
V
DDEXT
I/O SIGNALS
A
VDD
GND
*
KEY
123456789101112 1413
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Pin Descriptions
Pin Type
State During and
After Reset Description
AD15–0 I/O/T
(pu)
Three-state with
pull-up enabled
Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor.
RD
O
(pu)
Three-state, driven
high
1
Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or
16-bit data from an external memory device. When AD15–0 are ags, this pin remains
deasserted. RD has a 22.5 kΩ internal pull-up resistor.
WR O
(pu)
Three-state, driven
high
1
Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or
16-bit data to an external memory device. When AD15–0 are ags, this pin remains
deasserted. WR has a 22.5 kΩ internal pull-up resistor.
ALE O
(pd)
Three-state, driven
low
1
Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives
a new address on the parallel port address pins. On reset, ALE is active high. However,
it can be recongured using software to be active low. When AD15–0 are ags, this
pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor.
FLAG3–0 I/O/A Three-state Flag Pins. Each ag pin is congured via control bits as either an input or output. As
an input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx
and the TIMEXP signals.
DAI_P20–1 I/O/T
(pu)
Three-state with
programmable
pull-up
Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
The SRU conguration registers dene the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The conguration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the serial ports, input data port, precision clock gener-
ators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins
have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can
be disabled in the DAI_PIN_PULLUP register.
SPICLK I/O
(pu)
Three-state with
pull-up enabled
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of baud
rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active
during data transfers, only for the length of the transferred word. Slave devices ignore
the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted
out on one clock edge and sampled on the opposite edge of the clock. Clock polarity
and clock phase relative to data are programmable into the SPICTL control register
and dene the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor.
ADSP-21366KBCZ136-BALL, DSP BGA, sheet 1 of 2
To Next Page
Loading...
