Bose T1 ToneMatch - Page 61

61
IC Diagrams
AT45DB041D-SU, SPI Flash
Pin Congurations
Symbol Name and Function
Asserted
State Type
CS
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the de vice will be deselected
and normally be placed in the standby mode (not Deep Powe r-Down mode), and the output pin (SO) will be in a
high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to
end an operation. When ending an internally self-timed operat ion such as a program or erase cycle, the device
will not enter the standby mode until the completion of the operation.
Low Input
SCK
Serial Clock: This pin is used to provide a clock to the device and is used to control the ow of data to and from
the device. Command, address, and input data present on t he SI pin is always latched on the rising edge of SCK,
while output data on the SO pin is alwa ys clocked out on the falling edge of SCK.
– Input
SI
Serial Input: The SI pin is used to shift data into the device . The SI pin is used for all data input including
command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. If the SER/BYTE
pin is always driven low, the SI pin should be a “no connect”.
– Input
SO
Serial Output: The SO pin is used to shift data out from the de vice. Data on the SO pin is always clocked out on
the falling edge of SCK. If the SER/BYTE
pin is always driven low, the SO pin should be a “no connect”.
– Output
WP
Write Protect: When the WP pin is asserted, all sectors s pecied for protection by the Se ctor Protection Register will
be protected against program and erase operations regardless of whether the Enable Sector Protection command
has been issued or not. The WP pin functions independently of the softwar e controlled protection method. After the
WP
pin goes low, the content of the Sect or Protection Regist er cannot be modied.
If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore
the command and perform no operation. The device will return to the idle state once the CS pin has been
deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be
recognized by the device when the WP
pin is asserted.
The WP pin is internally pulled-high and may be left oating if hardware controlled protection will not be used.
However, it is recommended that the WP
pin also be externally connected to V
CC
whenever possible.
Low Input
RESET
Reset: A low state on the reset pin (RESET ) will terminate the operation in progress and reset the internal state
machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET
pin. Normal operation can resume once the RESET
pin is brought back to a high level.
The device incorporates an internal power-on rese t circuit, so there are no restrictions on the RESET pin during
power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high
externally.
Low Input
V
CC
Device Power Supply: The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
–Power
GND Ground: The ground reference for the power supply. GND should be connected to the system ground. – Ground
Block Diagram
SOIC Top View
1
2
3
4
8
7
6
5
SI
SCK
RESET
CS
SO
GND
VCC
WP
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER 2 (256/264 BYTES)BUFFER 1 (256/264 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
WP
SOSI