63
IC Diagrams
K6R4008V1D, SRAM
Clk Gen.
I/O1~I/O8
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
Row Select
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
1024 Rows
512 x 8 Columns
I/O Circuit
A10 A11 A12 A13 A14 A15 A16 A17 A18
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
36-SOJ
N.C
A
18
A
17
A
16
A
15
OE
I/O
8
I/O
7
Vss
Vcc
I/O
6
I/O
5
A
14
A
13
A
12
A
11
A
10
N.C
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
Vcc
Vss
I/O
3
I/O
4
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PIN FUNCTION
Pin Name Pin Function
A
0
- A
18
Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
I/O
1
~ I/O
8
Data Inputs/Outputs
V
CC
Power(+3.3V)
V
SS
Ground
N.C No Connection
PINOUT DIAGRAM (TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1IN+
1IN−
FEEDBACK
DTC
CT
RT
GND
C1
2IN+
2IN−
REF
OUTPUT CTRL
V
CC
C2
E2
E1
TOP VIEW
GND
V
CC
Reference
Regulator
C1
Pulse-Steering
Flip-Flop
C1
1D
DTC
CT
RT
PWM
Comparator
+
−
Error Amplifier 1
≈ 0.1 V
Dead-Time Control
Comparator
Oscillator
OUTPUT CTRL
(see Function Table)
0.7 mA
E1
C2
E2
+
−
Error Amplifier 2
1IN+
1IN−
2IN+
2IN−
FEEDBACK
REF
6
5
4
1
2
16
15
3
13
8
9
11
10
12
14
7
Q1
Q2
0.7 V
FUNCTIONAL BLOCK DIAGRAM
FUNCTION TABLE
INPUT TO
OUTPUT FUNCTION
OUTPUT CTRL
V
I
= GND Single-ended or parallel output
V
I
=V
ref
Normal push-pull operation
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
V
CC
6A
6Y
5A
5Y
4A
4Y
FUNCTION TABLE
(EACH INVERTER)
INPUT OUTPUT
AY
HL
LH
YA
LOGIC DIAGRAM, EACH INVERTER
PINOUT DIAGRAM
SN74LVCU04A, Hex inverter
TL494, PWM Controller
To Next Page
Loading...
