65
IC Diagrams
TAS1020B, USB Streaming Controller
Functional Block Diagram
8052 Core
I
2
C
Control
8K ROM
6016 Byte RAM
USB Serial
OSC
PLL
ACG
Suspend
/Resume
Logic
I
2
C Bus
C–Port
Port–3 Port–1
USB
SOF
6 MHz
Interface
Engine
CODEC
Interface
1520 Byte
SRAM
UBM DMA
Global
Control/Status
Registers
Terminal Assignments
23
P1.1
P1.0
NC
DV
DD
NC
P3.5
P3.4
P3.3
DV
SS
P3.2/XINT
P3.1
P3.0
24
23
22
21
20
19
18
17
16
15
14
13
4
37
38
39
40
41
42
43
44
45
46
47
48
CSCLK
CDATO
MCLKO1
MCLKO2
RESET
VREN
SDA
SCL
AV
SS
XTALO
XTALI
PLLFILI
567 8
P1.5
P1.4
P1.3
35 34 33 32 3136 30
CDATI
CSYNC
CRESET
CSCHNE
DV
TEST
EXTEN
RSTO
MCLKI
PUR
DP
DM
MRESET
28 27 2629
9101112
25
1
P1.2
P1.7
P1.6
DD
PLLFILO
(TOP VIEW)
AV
SS
DV
DD
DV
DD
DV
SS
TAS1020B
Terminal Functions
TERMINAL
NAME
PIN
TYPE
NO.
I/O DESCRIPTION
AV
DD
Power 2 3.3-V analog supply voltage
AV
SS
Power 45 Analog ground
CSCLK CMOS 37 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface used to clock
the CSYNC, CDATO, CDATI, CRESET,
AND CSCHNE signals.
CSYNC CMOS 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port
interface.
CDATO CMOS 38 I/O Codec port interface serial data out
CDATI CMOS 36 I/O Codec port interface serial data in
CRESET CMOS 34 I/O Codec port interface reset output
CSCHNE CMOS 32 I/O Codec port interface secondary channel enable
DP CMOS 6 I/O USB differential pair data signal plus. DP is the positive signal of the bidirectional USB differential
pair used to connect the TAS1020B device to the universal serial bus.
DM CMOS 7 I/O USB differential pair data signal minus. DM is the negative signal of the bidirectional USB differential
pair used to connect the TAS1020B device to the universal serial bus.
DV
DD
Power 8, 21, 33 3.3-V digital supply voltage
DV
SS
Power 4, 16, 28 Digital ground
EXTEN CMOS 11 I External MCU mode enable: Input used to enable the device for the external MCU mode
MCLKI CMOS 3 I Master clock input. An input that can be used as the master clock for the codec port interface or the
source for MCLKO2.
MCLKO1 CMOS 39 O Master clock output 1: The output of the ACG that can be used as the master clock for the codec port
interface and the codec.
MCLKO2 CMOS 40 O Master clock output 2: An output that can be used as the master clock for the codec port interface and
the codec used in I
2
S modes for receive. This clock signal can also be used as a miscellaneous
clock.
MRESET CMOS 9 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state
NC 20,22 Not used
P1.[0:7] CMOS 23, 24,
25, 26,
27, 29,
30, 31
I/O General-purpose I/O port [bits 0 through 1]: A bidirectional 8-bit I/O port with an internal 100 μA
active pullup
P3.[0:6] CMOS 13, 14,
15, 17,
18, 19
I/O General-purpose I/O port [bits 0 through 1]: A bidirectional I/O port with an internal 100 μA active
pullup
PLLFILI CMOS 48 I PLL loop filter input: Input to on-chip PLL from external filter components
PLLFILO CMOS 1 O PLL loop filter output: Output from on-chip PLL to external filter components
PUR CMOS 5 O USB data signal plus pullup resistor connect. PUR is used to connect the pullup resistor on the DP
signal from a high-impedance state to 3.3 V. When the DP signal is connected to 3.3-V the host PC
detects the connection of the TAS1020B device to the universal serial bus.
RESET CMOS 41 O General-purpose active-low output which is memory mapped
RSTO CMOS 12 O Reset output: An output that is active while the master reset input or the USB reset is active
SCL CMOS 44 O I
2
C interface serial clock
SDA CMOS 43 I/O I
2
C interface serial data
TEST CMOS 10 I Test mode enable: Factory test mode
VREN CMOS 42 O General-purpose active-low output which is memory mapped
XINT CMOS 15 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU
XTALI CMOS 47 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal
XTALO CMOS 46 O Crystal Output: Output from the on-chip oscillator to an external 6-MHz crystal
To Next Page
Loading...
