Casio MG-500 - Page 14

38
RD
R
Qut__|
Memory
read
signal
39 WR Out _| Memory write signal
40 ALE . Out Address Latch Enable.
Data bus PDO - PD7 become lower address (AO-
AT) bus.
41-48 | PFOPF7 : Out | Upper address (A8 - A15) bus
49-56 | PDO-PO7 - Infout_| Data bus
57 STOP : : Not used
L 58 voD - - +5 V source
GATE ARRAY F
The
gate
array
contains
counters
which
detects
the
frequency
of
string
vibration,
an
address
latch,
i
and
a
MIDI
data
buffer.
The
following
is
the
pin
function
of
the
gate
array.
Pin No. | Terminal Signal In/Out Function
1-10 | ADO-AD7 | ADO-AD7 | In/Out | Data bus
3,7__| GND 0G : Ground (0 V) source
11-20 | A0-A7 A0-A7 Out Lower address bus
12,23
|
CS2,CS1
Al5,A14
|
In
Built-in
counter
provides
frequency
data
from
data
bus when this terminal is Low and terminal CS1 is 1
High
21 voo1 vob : +5 V source
22 ALE ALE In Address Latch Enable signal. When this terminal is
High, the contents of data bus are latched and be-
come lower address bus (AO - A7).
24
WR
WR
In
When
Low,
peak
signals
from
the
strings
cannot
be
entered.
25
vob2
yoo
: +5
V source
26
RD
RD
In
__|
When
Low,
note
number is
provided
in data
bus.
27
Pt
PEAK
1
In
‘Ist
string’s
peak signal
input
28
st
SIG1
in
‘Ist
string’s
frequency
signal
input
29
P2
PEAK
2
In
2nd
string’s
peak
signal
input
30
82
SIG2
In__|
2nd
string’s
frequency
signal
input
31
P3
PEAK 3
in
3rd
string’s
peak
signal
input,
32
$3
SIG3
In
3rd string’s
frequency
signal
input
33
GND
0G
: Ground (0
V) source
[34
vod
vob
In
+5
V source
35
Pa
PEAK 4
In__|
Ath
string’s
peak signal
i
36
S4
sIG4
In
|
4th
string’s
frequency
signal
input
-2-