— 17 —
5-2. CPU (IC14)
Pin description
PIN NO PIN NAME I / O DESCRIPTION PIN NO PIN NAME I / O DESCRIPTION
1 PVPON I/O PR_VPON 41 WR I/O Write signal for Memoey
2 DRW I/O DRW 42 RAM_DIS I/O Chip select for RAM
3 WINDER I/O WINDER 43 ASTB I/O ASTB (to GATE Array)
4 Avss - VDD 44 MD_PGM I/O PGM (from KEY)
5 LATCH_R I/O H_LATCH_R 45 MD_RF I/O RF (from KEY)
6 LATCH_J I/O H_LATCH_J 46 MD_REG I/O REG (from KEY)
7 AVref1 IN VDD 47 MD_CAL I/O CAL (from KEY)
8 Rxd I/O Rxd for COM1 48 MD_X I/O X (from KEY)
9 TxD I/O TxD for COM1 49 CLK1.25M I/O CLOCK 1.25MHz (from GATE Array)
10 DSR I/O DSR for COM1 50 BUZZ I/O Buzzer signal
11 TAX_J I/O tax free switch (JAPAN only) 51 MD_Z I/O Z (from KEY)
12 VPP_OUT - Vss 52 F_BA11 - Vss
13 BAT_ON - Vss 53 F_BA12 - Vss
14 F_PGM - Vss 54 F_BA13 - Vss
15 PNE.S - Vss 55 F_BA14 - Vss
16 PUP_TST - VDD 56 F_BA15 - Vss
17 INIIT_SW - Vss 57 F_BA16 - Vss
18 VPP_ERR - Vss 58 R_PE IN Pepar end signal
19 AD0 I/O DATA BUS (AD0) 59 J_PE IN Pepar end signal (TE-2000 only)
20 AD1 I/O DATA BUS (AD1) 60 RESET IN RESET signal
21 AD2 I/O DATA BUS (AD2) 61 H_UP (R) IN H-UP signal for Printer
22 AD3 I/O DATA BUS (AD3) 62 H_UP (J) I/O H-UP signal for Printer (TE-2000 only)
23 AD4 I/O DATA BUS (AD4) 63 MT_IRQ I/O MT_IRQ (from GATE Array)
24 AD5 I/O DATA BUS (AD5) 64 PWD I/O Power supply status signal
25 AD6 I/O DATA BUS (AD6) 65 MD_OFF I/O OFF (from KEY)
26 AD7 I/O DATA BUS (AD7) 66 PAD_US - VDD
27 A8 I/O ADDRESS BUS (A8) 67 Vss0 - Vss
28 A9 I/O ADDRESS BUS (A9) 68 VDD1 - VDD
29 A10 I/O ADDRESS BUS (A10) 69 X2 IN CLOCK 5.0MHz
30 A11 I/O ADDRESS BUS (A11) 70 X1 IN CLOCK 5.0MHz
31 A12 I/O ADDRESS BUS (A12) 71 IC - Vss
32 A13 I/O ADDRESS BUS (A13) 72 XT2 IN CLOCK
33 Vss - Vss 73 XT1 IN CLOCK
34 A14 I/O ADDRESS BUS (A14) 74 VDD0 - VDD
35 A15 I/O ADDRESS BUS (A15) 75 AVref0 IN Power supply status signal
36 P60 - Vss 76 TEMP (R) I/O H_TEMP for Printer
37 P61 - Vss 77 TEMP (J) I/O H_TEMP for Printer (TE-2000 only)
38 P62 - Vss 78 VPIN I/O Power supply status signal
39 P63 - Vss 79 L_BAT I/O Power supply status signal
40 RD I/O Read signal for Memory 80 DWS I/O Drawer status signal
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