Chrontel CH7511B - Signal, Power, and Ground Layout; Thermal Exposed Pad Package

CHRONTEL AN-B014
206-1000-014 Rev. 1.7 2020-07-14 11
• Signal Wires, POWER and GND layout
Do not layout the wire or VIAs between the exposed thermal pad and the pin pads. Refer to Figure 13.
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Thermal exposed pad
Figure 13: Wires or vias are not allowed in these four areas
2.9 Thermal Exposed Pad Package
The CH7511B/7512B is available in a 68-pin QFN package with exposed thermal pad. The advantage of the exposed
thermal pad package is that the heat can be dissipated through the ground layer of the PCB more efficiently. When
properly implemented, the exposed thermal pad package provides a means of reducing the thermal resistance of the
CH7511B/7512B. Careful attention to the design of the PCB layout is required for good thermal performance. For
maximum heat dissipation, the exposed thermal pad of the package should be soldered to the PCB as shown in Figure
14.
Die
Exposed Pad
Solder
PCB
Pin
Figure 14: Cross-section of exposed thermal pad package