Chrontel CH7511B - User Manual

AN-B014
Application Note
206-1000-014 Rev. 1.7 2020-07-14 1
Chrontel
PCB Layout and Design Guide for CH7511B and CH7512B
1.0 INTRODUCTION
Chrontel’s CH7511B/7512B is an eDP/DP receiver that integrates LVDS Transmitter for the notebook/AIO display.
The CH7511B is designed to comply with the Embedded Display Port Specification 1.2 and the CH7512B is
designed to comply with the Display Port Specification 1.1a. The CH7511B/7512B provides support for two main
link lanes with data rate running at either 1.62Gb/s or 2.7Gb/s, and accepts data in 18-bit 6:6:6 or 24-bit 8:8:8 RGB
digital format. During system power-up, setting the power on/off sequence for a particular panel can be achieved
through the CH9904 Boot ROM registers. The CH7511B/7512B has incorporated a brightness control function to
interface with LCD backlight module. Brightness control commands sent through AUX Channel are dynamically
translated by the CH7511B/7512B and converted into the LCD backlight control signals.
The CH7511B/7512B can support 18-bit Single Port, 18-bit Dual Port, 24-bit Single Port and 24-bit Dual Port LVDS
outputs in both OpenLDI and SPWG bit mapping for LVDS application. The CH7511B/7512B supports LVDS
output up to 1920x1200.
This application note focuses only on the basic PCB layout and design guidelines for the CH7511B/7512B eDP/DP
Receiver with LVDS Transmitter. Guidelines in component placement, power supply decoupling, grounding, input
/output signal interface are discussed in this document.
The discussion and figures presented in this document are based on the 68-pin QFN (8x8 mm) package of the
CH7511B/7512B. Please refer to the CH7511B/7512B datasheet for details of the pin assignments.
2.0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS
Components associated with the CH7511B/7512B should be placed as close as possible to the respective pins. The
following will describe guidelines on how to connect critical pins, as well as the guidelines for the placement and
layout of components associated with these pins.
2.1 Power Supply Decoupling
The optimal power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor at each of the power
supply pins as shown in Figure 1. These capacitors (C1, C2, C3, C4, C5, C7, C8, C10, C11, and C12) should be
connected as close as possible to their respective power and ground pins using short and wide traces to minimize lead
inductance. Whenever possible, a physical connecting trace should connect the ground pins of the decoupling
capacitors to the CH7511B/7512B ground pins, in addition to ground vias.
2.1.1 Ground Pins
The CH7511B/7512B should be connected to a common ground plane to provide a low impedance return path for the
supply currents. Whenever possible, each of the CH7511B/7512B ground pins should be connected to its respective
decoupling capacitor ground lead directly, and then connected to the ground plane through a ground via. Short and
wide traces should be used to minimize the lead inductance. Refer to Table 1 for the Ground pin assignments.

Summary

Introduction to CH7511 B;7512 B

Component Placement and Design Considerations

Power Supply Decoupling

Guidelines for optimal power supply decoupling using ceramic capacitors placed close to power and ground pins.

Ground Pin Connections

Connect CH7511B/7512B ground pins to a common ground plane via short, wide traces and ground vias.

Power Supply Pins and Decoupling

Details on power supply pins (AVDD, DVDD, LVDD, VDDGPO) and their recommended decoupling configurations.

Internal Reference Pins

Configuration of the RBIAS pin for Band-gap Bias Voltage using a 10kΩ resistor to GND.

General Control Pins

Guidelines for RESETB, XI/XO, and REFCK pins for chip reset, reference clock input, and optional reference clock.

Serial Port Control Pins

Configuration of SPC0/SPD0 and SPC1/SPD1 for serial interface and Boot ROM updates.

Display Port Signal Pins

Guidelines for DP0P/N and DP1P/N signal routing, impedance, trace width, spacing, and length matching.

AUX Channel Pins

Configuration for AUXP and AUXN pins for half-duplex, bi-directional AC-coupled differential signal.

HPDET Output Pin

Usage of the HPDET pin to indicate device status and generate interrupt pulses.

LVDS Output Pins

Rules for routing LDCxP and LDCxN LVDS differential signals, including impedance, spacing, and length matching.

LED Status Indicators

GLED and OLED pins output control signals to indicate normal or abnormal operational status.

Backlight Control Pins

BLUP and BLDN pins are input pins to increase or decrease backlight brightness.

Power Down Control

PWRDN pin controls entering or exiting power down state via an active low pulse.

GPIO Pins for Panel Selection

GPIO[0:3] pins used as panel select signals, forming 16 combinations to match panel types.

PWM Output Pins

PWM_OUT0 and PWM_OUT1 pins for outputting PWM signals with specified frequency and duty cycle ranges.

PWM Input Pin

PWM_IN pin for PWM input with Bypass or Duty Cycle Multiplication modes.

IRQ Pin for Interrupts

IRQ pin outputs interrupt signals when BLUP and BLDN are executing.

Reserved Pins

Reserved pin (pin 2) should be left open in the application.

Important Design Considerations

Key considerations for panel power, backlight power, and pull-up voltage.

LVDS Power Considerations

Attention to power supplied to LVDS backlight and panel, checking panel specifications.

Signal, Power, and Ground Layout

Guidelines for signal wire, power, and GND layout, avoiding wires/VIAs near the thermal pad.

Thermal Exposed Pad Package

Details on the 68-pin QFN package with exposed thermal pad for efficient heat dissipation.

Reference Design Example

Reference Design Schematics

Presentation of schematic diagrams for the CH7511B/7512B reference design.

Reference Board Bill of Materials (BOM)

Revision History

Disclaimer

Chrontel CH7511B Specifications

General

Input Voltage	3.3V
HDCP Support	Yes
Category	Receiver
Operating Temperature	0°C to 70°C
Audio Output	I2S
Resolution Support	480p, 720p, 1080p, 4K
Color Depth	24-bit