EasyManua.ls Logo

Clevo N141ZU - Page 58

Clevo N141ZU
98 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Schematic Diagrams
B - 8 Processor 6/12
B.Schematic Diagrams
Processor 6/12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Top Swap Override
STP_A16OVR
LOW = Disable (Default)
STRAP PIN
HIGH =Enable Top Swap mode
I2C Address: 0x2C
STRAP PIN
Flash Descriptor Security Overide
Low = Enable security measures defined in the Flash Descriptor. (Default)
High = Disable Flash Descriptor Security (override)
㓦伖
BOT
㉮味⎗㉱䶂⛘㕡
For BIOS Debug
HIGH
LOW W/O TBT
W/TBT
TBT Detect
N13/N14 /N15 BOARD ID
GPP_D11 HIGH =N13/N14
LO =N15
HIGH = eDPGPP_G0
PANEL Type Detect
D02 Change GPIO FOR RTD3
D02 ADD RTD3 3G
D02 Check RVL
D02 Change GPIO FOR RTD3
D02
枸䔁
D02 BOM CHANHE
3.3VS
3.3VS
3.3VS
3.3VA
3.3VA
VDD3
3.3VS
3.3VS
3.3VS
3.3VA
3.3VA
SB_BLON 17
HDA_BITCLK25
HDA_SDIN025
HDA_SDOUT25
AZ_RST#_R25
PCH_SPKR25
HDA_SYNC25
CNVI_RGI_DT27
CNVI_BRI_DT27
CNVI_RGI_RSP27
CNVI_BRI_RSP27
SWI#7,26
CNVI_CLKREQ27
CNVI_RST#27
TBTA_HRESET 23
SATA_PWR_EN FROM PCH 29
PS8338B_PCH 18
PS8338B_SW 18
LIGHT_KB_DET# 26,31
ASM1543_I_SEL0 22
ASM1543_I_SEL1 22
ME_WE26
GPPC_DMIC_CLK31
GPPC_DMIC_DATA31
TPM_PIRQ#30
T_SDA31
T_SCL31
RTD3_3G_PWR_EN 27
RTD3_PCIE_WAKE# 20
TBT_PERST_N 20
SSD_PWR_DN# 28
GPP_C12_RTD3 28
SWI# 7,26
Title
Size Document Number Rev
Date: Sheet
of
6-71-N13Z0-D02
D02
[07] WHL U F,G/20 GPIO/HDA
A3
745Monday, September 17, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N140ZU
Title
Size Document Number Rev
Date: Sheet
of
6-71-N13Z0-D02
D02
[07] WHL U F,G/20 GPIO/HDA
A3
745Monday, September 17, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N140ZU
Title
Size Document Number Rev
Date: Sheet
of
6-71-N13Z0-D02
D02
[07] WHL U F,G/20 GPIO/HDA
A3
745Monday, September 17, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N140ZU
T36
R292 *0_04
R536 *10K_04
R214 *10K_04
R280 10K_04 W /O-TBT
R258 *100K_04
R266 *10K_04
T16
R491 *1K_04
R288 *10K_04
C403 *10p_25V_NPO_02
R535 *10mil_04
R220 *20K_04
R256 *10K_04
R497 33_04
R499 33_04
R278 *0_04
T34
T21
T30
T22
R279 *0_04
R493 1K_04
R219 100K_04
D22 RB751S-40H
A C
R498 33_04
R518 1K_04
7 of 20
U24G
WHL_U_IP_CCG/BGA
GPP_G4/SD_DATA3
CN35
I2S1_SFRM/SNDW2_CLK
BL37
GPP_D19/DMIC_CLK0/SNDW4_CLK
CP24
GPP_A16/SD_1P8_SEL
BY31
HDA_BCLK/I2S0_SCLK
BN37
HDA_SDO/I2S0_TXD
BN36
GPP_G7/SD_WP
CK34
GPP_D17/DMIC_CLK1/SNDW3_CLK
CK25
GPP_G5/SD_CD#
CH35
SD_1P8_RCOMP
CK33
GPP_G2/SD_DATA1
CL36
HDA_SYNC/I2S0_SFRM
BN34
HDA_RST#/I2S1_SCLK/SNDW1_CLK
BL35
GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
CH29
HDA_SDI0/I2S0_RXD
BN35
GPP_G6/SD_CLK
CK36
GPP_D20/DMIC_DATA0/SNDW4_DATA
CN24
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BW36
HDA_SDI1/I2S1_RXD/SNDW 1_DATA
BL36
SD_3P3_RCOMP
CM34
GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
CH32
GPP_G3/SD_DATA2
CM35
GPP_D18/DMIC_DATA1/SNDW3_DATA
CJ25
GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
CJ32
GPP_B14/SPKR
CF35
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO
CH30
GPP_G0/SD_CMD
CH36
GPP_D23/I2S_MCLK
CK23
I2S1_TXD/SNDW2_DATA
BL34
GPP_G1/SD_DATA0
CL35
R237 200_1%_04
T51
R529 *10K_04
R287 *10K_04
R531 *10K_04
R252 10K_04 EDP
R235 *10K_04W /TCM
T23
R530 *0_04
R495 *10K_04
R238 *10K_04W /O-TCM
6 of 20
U24F
WHL_U_IP_CCG/BGA
GPP_H11/I2C5_SCL/ISH_I2C2_SCL
CJ29
GPP_C22/UART2_RTS#
CN12
GPP_B21/GSPI1_MISO
CC30
GPP_H9/I2C4_SCL
CJ31
GPP_H8/I2C4_SDA
CJ30
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#
CM23
GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#
CA32
GPP_C20/UART2_RXD
CR12
GPP_D14/ISH_UART0_TXD
CN23
GPP_C23/UART2_CTS#
CM12
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
CR24
GPP_B22/GSPI1_MOSI
CA30
GPP_C19/I2C1_SCL
CJ12
GPP_C18/I2C1_SDA
CK12
GPP_C13/UART1_TXD/ISH_UART1_TXD
CH12
GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
BW37
GPP_H7/I2C3_SCL
CH28
GPP_H6/I2C3_SDA
CH27
GPP_D6/ISH_I2C0_SCL
CH20
GPP_F6/CNV_RGI_DT
CG19
GPP_C12/UART1_RXD/ISH_UART1_RXD
CG12
GPP_B17/GSPI0_MISO
CE27
GPP_A7/PIRQA#/GSPI0_CS1#
CC32
GPP_F4/CNV_BRI_DT
CJ20
GPP_D8/ISH_I2C1_SCL
CJ22
GPP_D13/ISH_UART0_RXD
CM24
GPP_B16/GSPI0_CLK
CE28
GPP_B15/GSPI0_CS0#
CC27
GPP_A23/ISH_GP5
CA34
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
CP22
GPP_D11/ISH_SPI_MISO/GSPI2_MISO
CM22
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
CR22
GPP_B19/GSPI1_CS0#
CA31
GPP_D5/ISH_I2C0_SDA
CK22
GPP_A22/ISH_GP4
CA35
GPP_C17/I2C0_SCL
CN11
GPP_B18/GSPI0_MOSI
CE29
GPP_H5/I2C2_SCL
CF29
GPP_H4/I2C2_SDA
CF27
GPP_D7/ISH_I2C1_SDA
CH22
GPP_C16/I2C0_SDA
CM11
GPP_A19/ISH_GP1
BW34
GPP_H10/I2C5_SDA/ISH_I2C2_SDA
CJ27
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
CN22
GPP_B20/GSPI1_CLK
CC29
GPP_A21/ISH_GP3
CA36
GPP_C21/UART2_TXD
CP12
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
CG14
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
CF12
GPP_A20/ISH_GP2
CA37
GPP_A18/ISH_GP0
BW35
GPP_F7/CNV_RGI_RSP
CH19
GPP_F5/CNV_BRI_RSP
CK20
R496 33_04
R281 10K_04 W /TBT
R679 0_04
T_SDA
T_SCL
SATA_PWR_EN FROM PCH
PCH_HDA_SPKR
HDA_RST#1
HDADOCKEN_N
PCH_HDA_SPKR
PCH_GPP_B16
PCH_GPP_B17
UART2_TXD
UART2_RXD
T_SDA
T_SCL
PCH_GPP_A12
PCH_GPP_B17
SD_RCOMP
UART2_RXD
UART2_TXD
PCH_GPP_B18
TBT Detect
BOARD_ID
EDP_DET
BOARD_ID
TBT Detect
PCH_GPP_B22
PCH_GPP_B22
PCH_GPP_D12
PCH_GPP_D12
Sheet 7 of 45
Processor 6/12

Table of Contents

Related product manuals