5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VDD3
DD_ON
3.3V
VDD5
5V
SUSC#
SUSB#
VDDQ
DDR1.35V_PWRGD
1.05_VCCST
VCCIO
3.3VS
5VS
VCCIO_PWRGD
ALL_SYS_PWRGD
DDR_VTT_PG_CTRL
VTT_MEM
VCCST_PWRGD
VCORE_PG
PM_PCH_PWROK
VCCSA
SYS_PWROK
PLT_RST#
VCORE
PM_PWROK
883us
3.518ms
226.525ms
35.564us
1.57ms
2.766ms
3.852ms
3.84ms
1.181ms
1.262ms
4.04ms
3.966ms
3.974ms
6.072ms
6.162ms
171.316ms
172.415ms
193.665ms
N850EJ Timing for G3 to S0/M0 [Non-Deep Sx Platform]
SUSB#_C10# 16.9ns
1.05DX_VCCSTG
14.096us
VCCSFR_OC
1.599ms
2.5V
1.915ms
( tCPU00:VCCST ramped and stable to VccST_PWRGD assertion >1ms , 2.66506ms )
( tCPU01: VDDQ ramped and stable to VccST_PWRGD assertion >1ms , 2.404ms )
( tCPU03 : VDDQ ramped and stable before VCCST stable < 25ms , 2.282ms )
( tCPU04:VCCST must always ramp with or earlier then VCCSTG. VCCST >= VCCSTG at all times during ramp > 0ns , 14.082ms )
( tCPU05 : VDDQ ramped and stable before VCCSA/VCCIO ramps > 100ns , 4.59ms/2.27ms )
( tCPU06 : VCCST ramped and stable before VCCSA/VCCIO ramps > 100ns , 6.148ms/3.826ms )
( tCPU07 : VCCSA ramped and stable before VCCIO stable Note: there is no timing requirement between )
H_PWRGD
106.876ms
( tCPU09 :VCCSA stable before PROCPWRGD > 1ms , 100.708ms )
( tCPU10 : VCCIO stable before PROCPWRGD > 1ms , 103.03ms )
( tCPU11 : VCCPLL stable before PROCPWRGD > 1ms , 106.856ms )
( tCPU12 : VCCPLL_OC stable before PROCPWRGD > 1ms , 105.277ms )
( tCPU16 : VCCST_PWRGD assertion to PCH_PWROK assertion > 0ns , 2.098ms )
( tCPU18 : DDR_VTT_CNTL (was DDR_PG_CTL) assertion to DDR VTT
supplied ramped and stable while PLTRST = H (de-asserted). 0us < t < 35us , 18.043us )
( tCPU19 : VccST_PWRGD assertion to DDR_VTT_CNTL (was DDR_PG_CTL) asserted. 0ns< t < 100ns , 66.2ns )
( tCPU26 : CPU_C10_GATE# de-assertion to VCCSTG stable 10us < t < 65us , 14us
Note: CPU_C10_GATE# de-assertion to VCCST also needs to meet max 65us on cold boot )
( tPCH28: SLP_S3# assertion to SLP_S4# assertion >30us , 35us )
( tPCH29: SLP_S3# assertion to PCH_PWROK deassertion >0ms , 6.072ms )
( tPCH33: PCH_PWROK high to PLTRST# de-assertion This timing is set by the PCH via Soft strap settings.
>99ms , 166ms )
( tPCH34 : All PCH Primary Rails should ramp up within this window. >80ms )
( tPLT04 : ALL_SYS_PWRGD assertion to PCH_PWROK This timing must be controlled on the platform > 1ms , 2.107ms )
( tPLT16 : VPP stable to VDDQ stable on power up > 30ms , -0.335ms )
This value is a suggested timing.
VCCIO_EN
12345
6
7
8
910
20 30 40 50 60 70 80 90 100 200
................
01 2 3 30..
100
......
0
( tPCH01: VccRTC stable (@90% of full value) to assertion RTCRST# high and SRTCRST# high. >9ms )
3.518ms
2.766ms
3.966ms
3.966ms
6.072ms
171.316ms
SLP_SUS#
RSMRST
PWR_BTN#
50.606ms
376.44ms
1.8VA
257.86us
1.05VA
1.207ms
3.3VA
2.7145ms
( tPCH03: VccPrimary stable (@95% of full value) to RSMRST# high >10ms )
30.5215ms
BIOS
烉
P2AFSP
EC
烉
P1C
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