Clevo N850EJ1 User Manual

Schematic Diagrams
PCH 1/9 B - 25
B.Schematic Diagrams
PCH 1/9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RTC Wake UP
For ITE IT8587B Test
ME+BIOS ROM 16MB
BOOT HALT
ENABLE:LOW
(INTERNAL WEAK PU)
CONSENT STRAP
ENABLE:LOW
(INTERNAL WEAK PU)
JTAG ODT
DISABLE:LOW
(INTERNAL WEAK PU)
SPI_* = 1"~6.5"
PESONALITY STRAP
ENABLE:LOW
(INTERNAL WEAK PU)
6-04-02564-492
GPP_G_14_GSXDIN:
DMI AC COUPLING FULL VOLTAGE MODE
WHEN SAMPLED LOW
Mismatch : +- 5 mils
Place GND Shield (4 mils)
Avoid the CLK signal
SPI0_MOSI SPI0_MISO
SPIO_IO2 SPIO_IO3
Enable CNVI
XTAL SELECT-1
HIGH -> 24 MHZ
LOW -> 38.4 MHZ
External pull-up is required.
Recommend 100K if pulled
up to 3.3V
嶇 BIOS 䡢 娵
GPIO
H: W / TPM
L: W/O TPM
9/21
9/22
Default
BOARD ID1
H: N85
L: N87
D02_12/04_H
D02_12/07_H
12/04
ESPI FLASH SHARING MODE
MASTER ATTACHED FLASH SHARING:LOW
SLAVE ATTACEHD FLASH SHARING:HIGH
(INTERNAL WEAK PD)
GPP_H12
D02_12/04_H
Close to PCH Side
D02_12/04_H
D02_12/04_H
Close to Connector Side Close to Connector Side
D02_12/04_H
D02_12/04_H
D02_12/18_H
D02_12/18_H
SPI_SI_M
SPI_SO_M
SPI_CS0#
SPI_SCLK_M
SPI_WP#
SPI_SI_R
SPI_SO_R
SPI_SCLK_R
SPI_CS_0#
SPI_IO2 SPI_IO3
SPI_SI_R SPI_SO_R
SPI_HOLD#
HSPI_MSI
HSPI_MSO
HSPI_SCLK
HSPI_CE#
SPI_SI_R
SPI_SO_R
SPI_CS_0#
SPI_SCLK_R
SPI_IO2
SPI_IO3
SPI_WP#
SPI_HOLD#
GPP_K_14_GSXDIN
EXTTS_SNI_DRV1
EXTTS_SNI_DRV0
TCH_PNL_INTR#
SML4ALERT#
SML4DATA
SML4CLK
GPP_H15
SML3CLK
GPP_H_12
SML2DATA
SML2CLK
INTRUDER#
SML3DATA
SPI_CS_0#
SPI_SO_R
SPI_SI_R
PCIECOMP_N
PCIECOMP_P
CNVI_BRI_DT
CNVI_RGI_DT
CNVI_RGI_DT CNVI_BRI_DT
SMI#_R
GPP_H15
BOARD_ID1
BOARD_ID2
TPM_DET
TPM_DET
BOARD_ID1
BOARD_ID2
GPP_H_12
CNVI_BRI_RSP
CNVI_RGI_RSP
SPI_SCLK_R
SPI_3.3V
VDD3
3.3VS
VCC_RTC
1V8_LDO
1V8_LDO
3.3VA
1V8_LDO
3.3VA
3.3VS
3.3VS
3.3VS
3.3VA
1V8_LDO
HSPI_CE#40
HSPI_MSI40
HSPI_MSO40
HSPI_SCLK40
VDD3 4,25,27,30,34,36,37,40,42,43,44,48,50,51,52,53
3.3VS 8,9,20,21,22,23,26,27,28,29,32,34,36,37,38,39,40,41,42,47,51,52,53
VCC_RTC 27,30
3.3VA 4,9,26,27,30,48
SPI_3.3V 30
PLT_RST# 17,25
CNVI_WGR_CLK_DP 34
CNVI_WGR_CLK_DN 34
CNVI_WGR_D0P 34
CNVI_WGR_D0N 34
CNVI_WGR_D1P 34
CNVI_WGR_D1N 34
CNVI_WT_CLK_DP 34
CNVI_WT_CLK_DN 34
CNVI_WT_D0P 34
CNVI_WT_D0N 34
CNVI_WT_D1P 34
CNVI_WT_D1N 34
CNVI_BRI_DT34
CNVI_BRI_RSP34
CNVI_RGI_DT34
CNVI_RGI_RSP34
CNVI_GNSS_PA_BLANKING34
CNVI_MFUART2_TXD34
CNVI_MFUART2_RXD34
GPP_J1_C10#43,48
1V8_LDO 30
GPIO4_1V8_MAIN_EN_R18
Title
Size Document Number Re v
Date: Sheet
of
6-71-N85J0-D01
D02B
[24] PCH 1/12-SPI/SMBUS
A3
24 63Friday, March 02, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Re v
Date: Sheet
of
6-71-N85J0-D01
D02B
[24] PCH 1/12-SPI/SMBUS
A3
24 63Friday, March 02, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Re v
Date: Sheet
of
6-71-N85J0-D01
D02B
[24] PCH 1/12-SPI/SMBUS
A3
24 63Friday, March 02, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R138 0_04
PJ48 *1mm
12
R434 33_04
R154 *10K_04
R430
*4.7K_04
R128
100K_04
R436 33_04
R165 *10K_04
R404
*4.7K_04
R129
*4.7K_04
R159 33_04
R699
20K_04
T35
C678
0.1u_10V_X7R_04
R163 10K_04
R460 33_04
R143 1M_04
R137200_1%_04
R130 *0402_short-p
T100
T112
R428150_1%_04
T22
R461 100K_04
R156 *10K_04
R462 100K_04
R435 *0402_short-p
T105
R405
100K_04
T23
T102
T24
R433 *0402_short-p
T103
R463 33_04
T121
R427 33_04
T108
R140
20K_04
R700
20K_04
R422 *0402_short-p
R155
*100K_04
W/O TPM
R438
10K_04
T101
R402
*20K_04
T37
1 OF 13
U34A
HM370
SPI0_CLK
AW47
GPP_D22/SPI1_IO3
BC17
SPI0_MISO
BA45
SPI0_MOSI
AU41
VSS
AL37
GPP_K14/GSXDIN
W46
GPP_D2/SPI1_MISO/SBK2_BK2
BE18
GPP_E3/CPU_GP0
AL47
GPP_H16/SML4CLK
AE43
GPP_B4/CPU_GP3
BC33
GPP_K16/GSXCLK
Y47
GPP_B3/CPU_GP2
BF32
GPP_E7/CPU_GP1
AM45
GPP_H17/SML4DATA
AJ46
SPI0_IO2
AY48
GPP_B13/PLTRST#
AV29
GPP_H14/SML3DATA
AD48
SPI0_IO3
BA46
SPI0_CS2#
AT40
GPP_H10/SML2CLK
AE48
GPP_H11/SML2DATA
AD47
SPI0_CS1#
AW48
GPP_K12/GSXDOUT
Y46
GPP_D21/SPI1_IO2
BD17
SPI0_CS0#
AY47
GPP_H18/SML4ALERT#
AE44
GPP_D0/SPI1_CS#/SBK0_BK0
BF19
GPP_D1/SPI1_CLK/SBK1_BK1
BE19
TP
AN35
RSVD2
R15
GPP_H15/SML3ALERT#
AC47
GPP_K15/GSXSRESET#
AA45
GPP_K13/GSXSLOAD
Y48
RSVD1
R13
GPP_H13/SML3CLK
AF47
GPP_D3/SPI1_MOSI/SBK3_BK3
BF18
GPP_H12/SML2ALERT#
AB47
GPP_A11/PME#/SD_VDD2_PWR_EN#
BE36
INTRUDER#
BB44
R164
10K_04
TPM
R459 0_04
R432
*1K_04
RN5
*10K_8P4R_04
1
2
3
4 5
6
7
8
U38
GD25B127DSIGR
CE#
1
SO
2
WP#
3
VSS
4
SI
5
SCK
6
HOLD#
7
VDD
8
R139200_1%_04
R350100_1%_04
R158200_1%_04
R703
100K_04
R431
*4.7K_04
R464 33_04
13 OF 13
U34M
HM370
GPP_J_2
AW3
GPP_J_3
AT10
GPP_J_4_CNV_BRI_DT_UART0_RTSB
AV4
CNV_WR_CLKN
BD4
CNV_WR_CLKP
BE3
CNV_WR_D0N
BB3
CNV_WR_D0P
BB4
CNV_WR_D1N
BA3
CNV_WR_D1P
BA2
CNV_WT_CLKN
BC5
CNV_WT_CLKP
BB6
CNV_WT_D0N
BE6
CNV_WT_D0P
BD7
CNV_WT_D1N
BG6
CNV_WT_D1P
BF6
CNV_WT_RCOMP
BA1
GPPJ_RCOMP_1P81
BD1
GPPJ_RCOMP_1P82
BE1
GPPJ_RCOMP_1P83
BE2
GPP_J0/CNV_PA_BLANKING
AV6
GPP_I11/M2_SKT2_CFG0
AP3
GPP_G1/SD_D0
BE9
GPP_G7/SD_WP
AV13
GPP_G5/SD_CD#
BE8
GPP_I12/M2_SKT2_CFG1
AP2
GPP_G2/SD_D1
BF8
PCIE_RCOMPN
B12
GPP_G3/SD_D2
BF9
GPP_J9/CNV_MFUART2_TXD
AU9
GPP_I13/M2_SKT2_CFG2
AN4
GPP_I14/M2_SKT2_CFG3
AM7
PCIE_RCOMPP
A13
GPP_G4/SD_D3
BG8
GPP_G6/SD_CLK
BD8
GPP_J1/CPU_VCCIO_PWR_GATE#
AY3
GPP_J7/CNV_RGI_RSP/UART0_CTS#
AV3
GPP_J8/CNV_MFUART2_RXD
AW2
GPP_J10
AV7
SD_RCOMP_3P3
BE4
RSVD3
Y36
GPP_J5/CNV_BRI_RSP/UART0_RXD
AY2
GPP_J6/CNV_RGI_DT/UART0_TXD
BA4
TP
AL35
RSVD2
Y35
SD_RCOMP_1P8
BE5
GPP_J11/A4WP_PRESENT
AR13
RSVD1
BC1
GPP_G0/SD_CMD
AW13
R161
20K_04
Sheet 24 of 60
PCH 1/9

Clevo N850EJ1 Specifications

General

Brand	Clevo
Model	N850EJ1
Category	Laptop
Language	English