5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Supports external Graphics
No integrated graphic and eDP
PU/PD for JTAG signals
S3 circuit:- DRAM PWR GOOD
logic
Haswell Processor 2/7 ( MISC,JTAG,CLK )
DDR3 Compensation Signals
Buffered reset to CPU
CAD Note: Capacitor need to be placed
close to buffer output pin
SVID Signals
Close to CPU side
CFG_RCOMP 12MIL
CFG2
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
CFG STRAPS FOR PROCESSOR
CFG[19:7]: Reserved configuration lanes. A test point may
be placed on the board for these lands.
CFG[4]: Reserved configuration lane. A test point may be
placed on the board for this lane.
Configuration Signals: The CFG signals have a default value of
'1' if not terminated on the board.
TRACE WIDTH 10MIL, LENGTH <500MILS
Processor Pullups/Pull downs
CPU SOCKET -- LGA1150
DPLL_REF_CLKP
H_PROCHOT #_RH_PROCHOT #
PCH_PLTRST_CPU
XDP_DBR_R
XDP_TDO_R
XDP_TRST#
XDP_TCLK
H_CPUP WRGD
PMSYS_PWRGD_BUF
H_CAT ERR#
SM_RCOM P_0
SM_RCOM P_1
SM_RCOM P_2
CPU_RS T#
DPLL_REF_CLKN
H_PROCHOT #
H_THRMT RIP#_R
XDP_TMS
XDP_TDI_R
XDP_TDO_R
CPU_RS T#
SM_RCOM P_0
SM_RCOM P_1
SM_RCOM P_2
XDP_TCLK
XDP_TMS
XDP_TDO_R
XDP_TDI_R
XDP_PREQ#
XDP_BPM7
XDP_BPM6
XDP_BPM5
XDP_BPM4
XDP_BPM3
XDP_BPM2
XDP_BPM1
XDP_BPM0
XDP_DBR_R
XDP_PRDY#
TESTLO_P6
CFG_RCOMP
TESTLO_N5
CFG7
CFG4
H_CPU_S VIDDAT
H_CPU_S VIDALRT# H_CPU_S VIDALRT#_R
H_CPU_S VIDCLK
PMSYS_PWRGD_BUF_RPMSYS_PWRGD_BUF
H_CPU_S VIDALRT#
H_CPU_S VIDCLK
H_CPU_S VIDDAT
DPLL_REF_CLKN
DPLL_REF_CLKP
VCC_SENSE_R
VSS_SENSE_R
VSS_SENSE_R
VCC_SENSE_R
CFG2
CFG5
CFG6
CFG3
PWR_DEBUG#
XDP_TRST#
CFG13
CFG14
CFG15
CFG17
CFG16
CFG19
CFG18
CFG8
CFG9
CFG11
CFG12
CFG0
CFG1
H_CPU_S VIDALRT#_R
CFG10
PWR_ DEBUG#
H_PROCHOT #
H_CPUP WRGD
3.3V
VDDQ
3.3V
1.05VS
3.3VS
1.05VS
1.05VS
VCCIO_OUT
VCORE
VCCIOA_O UT
VCCST
1.05VS
VCORE
VCCIO_OUT
VCCIO_OUT
1.05VS20,24,40,46,6
VDDQ10,4 1,5,7,8 ,9
3.3V11,17,2,22,24,25,26,27,30,36,37,39,40,41,43,44
CLK_EXP_P21
CLK_EXP_N21
PLT_RST#15,18,39
3.3VS10,11,12,13,14,15,16,17,18,19,2,20,21,22,23,24,25,26,27,28,31,32,33,34,35,36,37,38,39,43,46,7,8,9
PM_DRA M_P WRGD17
SUSB12,14,15,41,42,43,44
H_PECI16,31
H_PROCHOT #46
H_THRMT RIP#16
H_CPUP WRGD17
VCCIO_OUT46,5,6
PCH_PLTRST_CPU16
H_PM_SYNC16
H_PROCHOT _EC31
H_CPU_S VIDDAT46
H_CPU_S VIDCLK46
H_CPU_S VIDALRT#46
CLK_DP NS_N 21
CLK_DP NS_P 21
SM_VREF8
VCORE_VSS_SENSE 46
VCORE_VCC_SENSE 46
VCORE46,47,5,6
VCCIOA_O UT2,5
H_SK TOCC#17
CFG132
VCCST6
Title
Size Documen t Number Rev
Date: Sheet
of
6-71-P7500-D03A
3.0
[03] Processor 2/5-CLK,MISC
A3
358Wednesday, October 29, 2014
!!DMFWP!DP/
SCHEM ATIC1
Title
Size Documen t Number Rev
Date: Sheet
of
6-71-P7500-D03A
3.0
[03] Processor 2/5-CLK,MISC
A3
358Wednesday, October 29, 2014
!!DMFWP!DP/
SCHEM ATIC1
Title
Size Documen t Number Rev
Date: Sheet
of
6-71-P7500-D03A
3.0
[03] Processor 2/5-CLK,MISC
A3
358Wednesday, October 29, 2014
!!DMFWP!DP/
SCHEM ATIC1
R508 *1K_04R508 *1K_04
R491 1K_04R491 1K_04
R487 1K_04R487 1K_04
C544 *0.1u_16V_Y5V_04C544 *0.1u_16V_Y5V_04
R490 *0_04R490 *0_04
R469 1K_04R469 1K_04
HASWELL
5OF10
?
?
REV = 1.1
U42E
3H993821-4M41-02H
HASWELL
5OF10
?
?
REV = 1.1
U42E
3H993821-4M41-02H
CFG[2]
AA36
CFG[4]
V39
CFG[5]
U39
CFG[6]
U40
CFG[7]
V38
CFG[9]
Y35
CFG[10]
AA34
CFG[11]
V37
CFG[12]
Y34
CFG[13]
U38
CFG[14]
W34
CFG[15]
V35
CFG[17]
Y36
CFG[16]
Y37
CFG[19]
V36
CFG[18]
W36
TCK
D39
TDI
F38
TDO
F39
TESTLO_N5
N5
RSVD_TP_K8
K8
RSVD_TP_J10
J10
BPM#[0]
G39
BPM#[1]
J39
BPM#[2]
G38
BPM#[3]
H37
BPM#[4]
H38
BPM#[5]
J38
BPM#[7]
K37
BPM#[6]
K39
RSVD_M38
M38
RSVD_T35
T35
TESTLO_P6
P6
FC_K9
K9
RSVD_H15
H15
RSVD_H14
H14
RSVD_J9
J9
VCC_M8
M8
RSVD_AV2
AV2
RSVD_TP_J16
J16
PWR_DEBUG
N40
RSVD_TP_H16
H16
VSS_N39
N39
VSS_V7
V7
VSS_AB6
AB6
RSVD_TP_J8
J8
RSVD_TP_K13
K13
SM_RCOMP[0]
R1
SM_RCOMP[1]
P1
SM_RCOMP[2]
R2
RSVD_TP_AW2
AW2
RSVD_AB36
AB36
RSVD_TP_AV1
AV1
RSVD_AC8
AC8
VCOMP_OUT
P4
RSVD_U8
U8
RSVD_AB33
AB33
VSS_T8
T8
RSVD_M10
M10
RSVD_Y8
Y8
RSVD_L10
L10
RSVD_M11
M11
RSVD_L12
L12
RSVD_W8
W8
RSVD_R33
R33
VCC_SENSE
E40
RSVD_P33
P33
VSS_J11
J11
VSS_M9
M9
VSS_J7
J7
VSS_SENSE
F40
RSVD_N35
N35
DPLL_REF_CLK
W5
CFG_RCOMP
H40
VSS_N33
N33
TMS
E39
DPLL_REF_CLK#
W6
VIDSCLK
C38
VIDSOUT
C37
CFG[0]
AA37
SM_VREF
AB38
PECI
N37
PM_SYNC
P36
PWRGOOD
AB35
SM_DRAMPWROK
AK21
RESET
M39
VIDALERT
B37
CATERR
M36
PROCHOT
K38
THERMTRIP
F37
SKTOCC
D38
TRST
E37
PRDY
L39
PREQ
L37
DBR
G40
CFG[3]
W38
CFG[1]
Y38
CFG[8]
T40
BCLK#
V4
BCLK
V5
R568 0_04R568 0_04
R468 *10mil_shortR468 *10mil_short
R476 75_1%_04R476 75_1%_04
R475 100_1%_04R475 100_1%_04
R34 10_04R34 10_04
R486 *0_04R486 *0_04
R35 75_04R35 75_04
R482 0_04R482 0_04
R498 *1K_04R498 *1K_04
R516 *1K_ 04R516 *1K_ 04
R472 *51_04R472 *51_04
Q40
*MTN7002ZHS3
Q40
*MTN7002ZHS3
G
DS
U44
*MC74VHC1G08DFT1G
U44
*MC74VHC1G08DFT1G
1
2
5
4
3
R470 51_04R470 51_04
R33 10_04R33 10_04
R515 10K_04R515 10K_04
R41 *100_04R41 *100_04
R511 *1K_04R511 *1K_04
R473 49.9_1%_04R473 49.9_1%_04
R571
1.82K_1%_04
R571
1.82K_1%_04
R501 *10K_04R501 *10K_04
R569
3.32K_1%_04
R569
3.32K_1%_04
R44 *100_04R44 *100_04
R471 1K_04R471 1K_04
Q35
MTN7002ZHS3
Q35
MTN7002ZHS3
G
DS
R566 0_04R566 0_04
R572
*100K_04
R572
*100K_04
R39 44.2_1%_04R39 44.2_1%_04
R38 110_1%_04R38 110_1%_04
R485
100K_04
R485
100K_04
R556
*100K_04
R556
*100K_04
R31 *51_04R31 *51_04
R36 51_04R36 51_04
R474 100_1%_04R474 100_1%_04
C508
47P_50V_NPO_04
C508
47P_50V_NPO_04
R494 *1K_1%_04R494 *1K_1%_04
R479 49.9_1%_04R479 49.9_1%_04
C556
*0.1u_16V_Y5V_04
C556
*0.1u_16V_Y5V_04
R567
*39_04
R567
*39_04
R43 0_04R4 3 0_04
R500 *1K_04R500 *1K_04
R484 51_04R484 51_04
R45 *90.9_1%_04R45 *90.9_1%_04
R503 0_04R503 0_04
R467 49.9_1%_04R467 49.9_1%_04
R502 150_1%_04R502 150_1%_04
R555
*200_04
R555
*200_04
R495 *2K_1%_04R495 *2K_1%_04
R42 0_04R42 0_0 4
R40 51_04R40 51_04
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