Clevo W370ET - POWER ON SEQUENCE

Schematic Diagrams
B - 56 POWER ON SEQUENCE
B.Schematic Diagrams
POWER ON SEQUENCE
Sheet 55 of 55
POWER ON
SEQUENCE
RTCRST#
VCCRTC
5V
3V
PWRBTN#
SLP_S3# (SUSB)
SLP_S4# (SUSC)
DD_ON#
1.5VS
1.05VS
DELAY_PWRGD
H_VTTPWRGD(ALL_SYS_PWRGD)
IMVP_VR_EN
CPU SVID BUS
1.8VS(VccPLL)
setVID
SLOW
packet
PLT_RST#
W370ET/ W350ET POWER SEQUENCE
2ms
3.2ms
SUS_PWR_DN_ACK
1.6mS
1.5V
13.7mS
7mS
11mS
8mS
1.25ms
4.38mS
1.6mS
0.85VS
1.05VS_VTT
3.3VS
56ms
20us
1.95mS
1.7mS
1.5VS _CPU
VCORE
11mS
VGFX_CORE
13.7mS
136mS
14.2mS
239mS
217mS
136mS
H_CPUPWGD
241mS
241mS
2.7mSVTT_MEM(0.75V)
S4_STATE#
5VS
DRAMPWROK
SYS_PWROK
SPEC MAX500us
SPEC MIN MAX5ms
A
C
K
SPEC MAX50us
SPEC MIN50us~MAX2000us
VCORE
SPEC MAX5ms
ACPRESENT
RSMRST#
2mS
229ms
37.5ms
MVP_PWRGD (VR_Ready)
IMVP_VR_EN
PM_PCH_PWROK (APWROK)