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Clevo W370ET - Ivy Bridge 2;7

Clevo W370ET
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Schematic Diagrams
B - 4 Ivy Bridge 2/7
B.Schematic Diagrams
Ivy Bridge 2/7
CLK_DP_P 22
CLK_DP_N 22
H_PROCHOT#43,4 5
H_THRMTRIP#26
H_PECI22,26,37
H_PM_SYNC23
3.3VS9,10,11,12,21,22,23,24,25,26,27, 28,30,31,33,34,35,36,37, 38,43,45
PLT_RST#25,31
H_CPUPWRGD26
DDR3_DRAMRST# 9,10,11
DRAMRST_CNTRL 6,22
H_SN B_IVB#26
H_PROCHOT#_EC37
SUSB38,40,41,42
1.8VS_PWRGD23,40
PM_DRAM_PWRGD23
1.5V6,9,10, 11,28,38,41
H_PROCHOT#
H_CPUPWRGD_R
R456
*100K_04
XD P_ T C L K
S3 circuit:- DRAM PWR GOOD logic
R470 *10mil_short
CAD Note: Capacitor need to be placed
close to buffer output pin
TRACE WIDTH 10MIL, LENGTH <500MILS
H_CPUPWRGD_R
Processor Pullups/Pull downs
H_PROCHOT#
BUF_CPU_RST#
H_CATERR#
XD P_ T D O_ R
XDP_DBR_R
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
XDP_TRST#
XDP _TC LK
VDDPWRGOOD_R
H_PROCHOT#_D
XDP _TMS
H_PROCHOT#
CPUDRAMRST#
XDP_PREQ#
XDP _TD I _R
XDP _TD O_ R
SKTOCC#
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
DDR3 Compensation Signals
BUF_CPU_RST#
R332 *0_04
SM_RCOMP_1
SM_RCOMP_0
SM_RCOMP_2
6-86-27988-004 T2 PZ98821-362B-01H
6-86-27988-005 GF 479890730
XDP_PRDY#
R221 *1.5K_1%_04
PMSYS_PWRGD_BUF
XD P_ T D I _ R
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
Buffered reset to CPU
CPUDRAMRST#
S3 circuit:- DRAM_RST# to memory
should be high during S3
R474
*39_04
C29
47p_50V_NPO_04
R219
75_04
R218
100K_0 4
R330
1K_04
R215 62_04
Q31
*MTN7002ZHS3
G
DS
R220 1K_04
S
D
G
Q13B
MTDN 7002Z HS 6R
5
34
R24 *10mil_short
R222
*7 50_1%_04
R224 43.2_1%_04
R256 10K_04
R461
*200_04
S
D
G
Q13A
MTDN7002ZHS6R
2
61
Q12
MTN7002ZHS3
G
DS
R19 56_1%_04
RN5 56_8P4R_04
1
2
3
45
6
7
8
R351 200_1%_04
R84 130_1%_04
R217
10K_04
XD P_ T MS
C579
0.047u_10V_X7R_04
XDP_DBR_R
R478
200_1%_04
PU/PD for JTAG signals
XDP_TRST#
H_SNB_IVB#
XDP_PREQ#
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U15B
T2
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_D RAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCL K
A28
DPLL_REF_CLK#
A15
DPL L_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
TH ERMTR IP #
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY#
AP29
PRE Q#
AP27
TC K
AR26
TMS
AR27
TR ST#
AP30
TD I
AR28
TD O
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R329 1K_04
R388 140_1%_04
Q21
MTN7 002Z HS3
G
DS
C463
68p_50V_NPO_04
R349 25.5_1%_04
C651
*0.1u_16V_Y5V_04
PMSYS_PWRGD_BUF
R39*51_04
R337
4.99K_1%_04
R26351_04
U31
*MC7 4VHC1G 08DFT1G
1
2
5
4
3
R216
100K_04
3.3V S
1.5V
1.05VS_VTT
3.3V
1.5V S_CPU
3.3V
1.05 VS_VTT
1.05VS_VTT
R223 *1 0mil_s hort
1.05VS_VTT2,5,23,26,27,28, 38
3.3VS
CLK_EXP_N 22
CLK_EXP_P 22
1.5VS_CPU6,38,41
3.3V2,6,12,19,21,22, 23,25,26,27, 28,30,31,32, 36,38,40,41,42
Sheet 3 of 55
Ivy Bridge 2/7

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