Clevo W510TU - AU6259-JGF Schematic

Schematic Diagrams
B - 16 AU6259-JGF
B.Schematic Diagrams
AU6259-JGF
Sheet 15 of 42
AU6259-JGF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USBH_V33 USBH_V33
USBH_V33 USBH_V33
USBH_V33
USBH_V33
USBH_RREF USBH_V18
USBH_V18
BUS_PWREDN
USBH_XSCI
USBH_V33
USBH_XSCI
USBH_XSCO
USBH_XSCO
USBH_RST#
USBH_V18
USBH_V33
BUS_PWREDN
5VS5V
5V
USB_PN3 6
USB_PP3 6
USB_DP118
USB_DM118
USB_DM218
USB_DP218
USB_DM318
USB_DP318
USB_DP419
USB_DM419
Title
Size Document Number Rev
Date: Sheet
of
6-71-W5100-D02
2.0
[15] AU6259-JGF (USB HUB)
A4
15 35Friday, January 24, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
W510TU
Title
Size Document Number Rev
Date: Sheet
of
6-71-W5100-D02
2.0
[15] AU6259-JGF (USB HUB)
A4
15 35Friday, January 24, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
W510TU
Title
Size Document Number Rev
Date: Sheet
of
6-71-W5100-D02
2.0
[15] AU6259-JGF (USB HUB)
A4
15 35Friday, January 24, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
W510TU
port1 USB port
port2 USB port
port3 CCD
port4 mSATA
P/N: 6-22-12R00-1B0
'1' = Self Powered
'0' = Bus Powered
USB signal line trace:
1.Keep traces of USB bus D+ and D- the same length.
2.Achieve 90 ohm differential characteristic impedance.
3.Achieve 45 ohm common characteristic impedance.
4.Maintain parallelism between D+ and D-.
5.Do not route USB2.0 D+ and D- over the power plane split.
6.Do not route USB2.0 D+ and D- over the other high frequency signals.
7.It is preferred to route USB2.0 D+ and D- over ground layer.
8.It is preferred to route USB2.0 D+ and D- using single layer.
For more detail,see design guideline in design kit.
FROM SOC PORT 3
D02 modify
C68
12p_50V_NPO_04
C68
12p_50V_NPO_04
C78
0.1u_10V_X7R_04
C78
0.1u_10V_X7R_04
R24
47K_04
R24
47K_04
C80
0.1u_10V_X7R_04
C80
0.1u_10V_X7R_04
R30 *10mil_shortR30 *10mil_short
R37
10K_04
R37
10K_04
C55 0.1u_10V_X7R_04C55 0.1u_10V_X7R_04
R47 0_04R47 0_04
C69
4.7u_6.3V_X5R_06
C69
4.7u_6.3V_X5R_06
C58
12p_50V_NPO_04
C58
12p_50V_NPO_04
C46 0.1u_10V_X7R_04C46 0.1u_10V_X7R_04
C79
1u_6.3V_X5R_04
C79
1u_6.3V_X5R_04
12
3 4
X1
HSX321G_12Mhz
X1
HSX321G_12Mhz
C52
0.1u_10V_X7R_04
C52
0.1u_10V_X7R_04
C71
2.2u_6.3V_X5R_04
C71
2.2u_6.3V_X5R_04
R31
470K_04
R31
470K_04
R29 *10mil_shortR29 *10mil_short
C36
0.1u_10V_X7R_04
C36
0.1u_10V_X7R_04
R53 1M_04R53 1M_04
C37
0.1u_10V_X7R_04
C37
0.1u_10V_X7R_04
R40 680_04R40 680_04
R52 *0_04R52 *0_04
R70
*1_1%_06
R70
*1_1%_06
C32
1u_6.3V_X5R_04
C32
1u_6.3V_X5R_04
PVDD
3
XSCO
4
XSCI
5
DP2_DM
6
DP2_DP
7
AVDD
8
DP3_DM
9
DP3_DP
10
DP4_DM
11
DP4_DP
12
AVDD5V
15
BUS_PWREDN
17
ChipResetN
21
V33
16
AVDD
26
SUSPEND
19
DP1_DM
27
VDD
18
VDDH
22
V18
14
AVSS
23
UP_DM
24
UP_DP
25
AVDD
13
AVDD
1
UP_RREF
2
VDD
20
DP1_DP
28
Die Pad
29
U5
AU6259-JGF
U5
AU6259-JGF
R74
1_1%_06
R74
1_1%_06