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Describes the 80C51 CPU core with 1-T architecture.
Details the 16kB program memory with password protection.
Specifies the on-chip data memory size and organization.
Lists various power saving modes like power-down, idle, etc.
Specifies the operating frequency range up to 25 MHz.
Details interrupt sources, priority levels, and filtering.
Describes the 8-channel, 12-bit ADC with sampling rate.
Mentions the master/slave SPI serial interface with rate up to 12 MHz.
Details the TWI0/I2C0 and STWI (SI2C) interfaces.
Describes the DMA engine and its capabilities.
Lists the on-chip timers/counters including RTC and WDT.
Specifies the RF operating frequency from 127 to 1020 MHz.
Lists supported modulation methods like GFSK, MSK, OOK.
Specifies the data rate from 0.5 to 300 kbps.
Details the receiver sensitivity parameter.
Lists the receive current consumption.
Specifies the transmitting current consumption.
Specifies the operating supply voltage range.
Specifies the operating temperature range.
Mentions the QFN40 5x5 packaging.
Lists automatic meter reading as an application.
Lists home security and building automation as applications.
Lists wireless sensor networks and industrial monitoring.
Lists ISM band data communication as an application.
Summarizes the 8-bit CPU core and ultra-low power RF transceiver.
Lists the wide range of peripherals available on the device.
Lists the recommended operating conditions for the device.
Details the absolute maximum ratings to avoid device damage.
Describes the transmitter functionality and configuration.
Details the receiver architecture and features.
Explains the Power-on Reset mechanism.
Describes the crystal oscillator requirements.
Explains the LPOSC for sleep timer.
Describes the low battery detection function.
Details the RSSI measurement and comparison circuit.
Explains the PJD for FSK demodulation.
Describes the CDR systems for clock recovery.
Explains manual frequency hopping.
Discusses transceiver operating status and timing.
Details the CPU registers, including PSW.
Describes the CPU timing characteristics.
Explains different CPU addressing modes.
Describes the on-chip program flash memory organization.
Details the on-chip data RAM organization.
Explains XRAM access and usage.
States that off-chip external data memory is not supported.
Lists declaration identifiers for memory spaces.
Describes XRAM access using dual DPTR.
Explains XRAM access using XRPS register.
Details the DMA controller structure.
Explains the setup and operation of the DMA controller.
Details the DMA control registers.
Presents the system clock structure and sources.
Explains how to switch clock sources.
Describes the on-chip Clock Multiplier (PLL).
Details wake-up procedure using CKM.
Describes the clock control registers.
Details the WDT structure and functionality.
Explains WDT behavior in Idle and Power-down modes.
Describes the WDT control register.
Explains hardware options for WDT initialization.
Introduces the RTC module and its functions.
Lists and illustrates system reset sources.
Explains the power-on reset mechanism.
Describes the external reset functionality.
Explains how to trigger a software reset.
Details brown-out detection and reset.
Explains WDT reset functionality.
Describes reset due to illegal address access.
Explains the Brown-Out Detectors (BOD0, BOD1).
Explains various power saving modes.
Details the Power Control Register 0 (PCON0).
Describes the two main I/O groups and modes.
Details the I/O port registers and their configurations.
Explains alternate GPIO functions and redirection.
Lists all interrupt sources and their properties.
Details interrupt sources and their corresponding flags.
Explains how to enable/disable interrupts.
Describes the four-level interrupt priority scheme.
Explains the interrupt process and block conditions.
Details nINTx source selection and filtering.
Describes interrupt control registers like TCON and IE.
Explains Timer 0 and Timer 1 modes and registers.
Details Timer 2 modes, registers, and special functions.
Explains Timer 3 modes, registers, and special functions.
Provides global control for starting, reloading, and stopping timers.
Provides an overview of the Programmable Counter Array.
Describes the PCA timer/counter functionality.
Details the PCA compare/capture modules and their modes.
Explains various operation modes of the PCA modules.
Explains Serial Port 0 Mode 0 (synchronous communication).
Details Serial Port 0 Mode 1 (10-bit asynchronous communication).
Explains Serial Port 0 Modes 2 & 3 (11-bit asynchronous communication).
Describes frame error detection functionality in UART0.
Explains multiprocessor communication capabilities of UART0.
Details automatic address recognition feature in UART0.
Explains how to set and calculate baud rates for UART0.
Describes advanced features for Serial Port 0.
Details the S1BRG for generating UART1 clock.
Explains S1BRG configuration for UART operation.
Explains Serial Port 1 Mode 4 for SPI Master functionality.
Describes S1BRG operating in 8-bit Timer Mode.
Explains S1BRG operating in 16-bit Timer Mode.
Details the S1BRT for generating programmable clock output.
Shows common SPI master/slave configurations.
Provides guidance on configuring the SPI interface.
Explains SPI data modes including clock polarity and phase.
Details the configuration for SPI daisy-chain connection.
Describes the SPI control and status registers.
Lists the four operating modes for the TWI/I2C interface.
Describes miscellaneous TWI/I2C states and bus errors.
Provides guidance on using the TWI/I2C interface.
Describes TWI0/I2C0 registers like SIADR, SIDAT, SICON.
Shows the configuration of STAF and STOF detection.
Details the SID register (AUXR2).
Explains the beeper generator circuit and configuration.
Details the Keypad Interrupt structure.
Lists the special function registers for KBI operation.
Describes the GPL-CRC structure and operation.
Explains the GPL-BOREV structure for bit reversal.
Details the GPL registers related to CRC operation.
Shows the ADC block diagram and its components.
Explains ADC operation, including channels and conversions.
Describes the ADC control registers (ADCON0).
Shows the IVR block diagram.
Details the IVR register (PCON3).
Provides sample code to read prestored IVR values for ADC calibration.
Shows the flash memory configuration and partitioning.
Explains flash access modes for ISP/IAP operations.
Describes the ISP operation procedures and methods.
Explains the IAP functionality for non-volatile data storage.
Lists the registers relevant for ISP/IAP and Page-P access.
Lists and describes auxiliary SFRs mapped across pages.
Shows the SFR map covering pages 0 through F.
Lists SFR bit assignments for pages 0 through F.
Shows the SFR map specifically for Page P.
Lists SFR bit assignments for Page P.
Lists and describes various auxiliary SFR registers.
Describes the LOCK hardware option for security.
Explains the ISP-memory space configuration options.
Details the HWBS hardware option for boot source selection.
Explains the HWBS2 hardware option for reset-pin induced booting.
Describes the IAP-memory space configuration.
Shows the recommended power supply circuit with capacitors.
Details the external reset circuit configuration.
Explains the ICP and OCD interface circuits for debugging.
Describes the In-Chip-Programming (ICP) function.
Explains the On-Chip-Debug (OCD) function.
Lists instructions for data transfer operations.
Lists instructions for arithmetic operations.
Lists instructions for logic operations.
Lists instructions for boolean variable manipulation.
Lists instructions for program branching.
General| Brand | CMOSTEK |
|---|---|
| Model | CMT2380F17 |
| Category | Transceiver |
| Language | English |
