CMT2380F17
Rev0.1 | 261/347
and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used
to temporarily isolate TWI/ I2C from the bus.
21.1.4 Slave Receiver Mode
In the slave receiver mode, a number of data bytes are received from a master transmitter. Data transfer
is initialized as in the slave transmitter mode.
When SIADR and SICON have been initialized, TWI/ I2C waits until it is addressed by its own slave
address followed by the data direction bit which must be “0” (W) for TWI/ I2C to operate in the slave receiver
mode. After its own slave address and the W bit have been received, the serial interrupt flag (SI) is set and a
valid status code can be read from SISTA. This status code is used to vector to an interrupt service routine,
and the appropriate action to be taken for each of these status codes is detailed in the following operating flow
chart. The slave receiver mode may also be entered if arbitration is lost while TWI/ I2C is in the master mode
(see status 68H and 78H).
If the AA bit is reset during a transfer, TWI/ I2C will return a not acknowledge (logic 1) to SDA after the
next received data byte. While AA is reset, TWI/ I2C does not respond to its own slave address or a general
call address. However, the serial bus is still monitored and address recognition may be resumed at any time
by setting AA. This means that the AA bit may be used to temporarily isolate from the bus.
21.2 Miscellaneous States
There are two SISTA codes that do not correspond to a defined TWI/ I2C hardware state, as described
below.
S1STA = F8H
This status code indicates that no relevant information is available because the serial interrupt flag, SI, is
not yet set. This occurs between other states and when TWI/ I2C is not involved in a serial transfer.
S1STA = 00H:
This status code indicates that a bus error has occurred during a TWI/ I2C serial transfer. A bus error is
caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such
illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus
error may also be caused when external interference disturbs the internal TWI/ I2C signals. When a bus error
occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared by software.
This causes TWI/ I2C to enter the “not-addressed” slave mode (a defined state) and to clear the STO flag (no
other bits in SICON are affected). The TWI/ I2C0_SDA and TWI/ I2C0_SCL lines are released (a STOP
condition is not transmitted).
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