CMOSTEK CMT2380F17 - Page 5

CMT2380F17
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5.3.2 Indirect Addressing (IND) ...................................................................................................................... 49
5.3.3 Register Instruction (REG) .................................................................................................................... 49
5.3.4 Register-Specific Instruction .................................................................................................................. 49
5.3.5 Immediate Constant (IMM) .................................................................................................................... 49
5.3.6 Index Addressing................................................................................................................................... 49
6 Memory Organization ................................................................................................................................................ 50
6.1 On-Chip Program Flash ...................................................................................................................................... 50
6.2 On-Chip Data RAM ............................................................................................................................................. 51
6.3 On-chip Expanded RAM (XRAM) ........................................................................................................................ 52
6.4 Off-Chip External Data Memory access .............................................................................................................. 52
6.5 Declaration Identifiers in a C51-Compiler ............................................................................................................ 52
7 XRAM Access ............................................................................................................................................................ 54
7.1 MOVX on 16-bit Address with dual DPTR ........................................................................................................... 54
7.2 MOVX on 8-bit Address with XRPS .................................................................................................................... 55
8 Direct Memory Access Controller (DMA) ................................................................................................................. 57
8.1 DMA Structure ..................................................................................................................................................... 57
8.2 DMA Operation ................................................................................................................................................... 58
8.2.1 DMA Transfer Types .............................................................................................................................. 58
8.2.2 DMA Transfer Mode .............................................................................................................................. 59
8.2.3 Transfer Count & Address Pointer ......................................................................................................... 59
8.2.4 Start a DMA Transfer ............................................................................................................................. 60
8.2.5 Suspend or Stop DMA Transfer ............................................................................................................. 60
8.2.6 DMA Interrupt ........................................................................................................................................ 60
8.2.7 DMA Loop Mode ................................................................................................................................... 61
8.2.8 Error Handling in DMA .......................................................................................................................... 61
8.2.9 Data Copied to CRC16 ......................................................................................................................... 61
8.2.10 Timer 5 & Timer 6 .................................................................................................................................. 61
8.3 DMA Register ...................................................................................................................................................... 62
8.4 Timer5 Register ................................................................................................................................................... 64
8.5 Timer 6 Register .................................................................................................................................................. 66
9 System Clock ............................................................................................................................................................. 68
9.1 Clock Structure .................................................................................................................................................... 68
9.2 Clock Source Switching ...................................................................................................................................... 69
9.3 On-chip CKM (PLL) ............................................................................................................................................. 69
9.4 Wake-up clock from CKM.................................................................................................................................... 69
9.5 Clock Register ..................................................................................................................................................... 70
10 Watch Dog Timer (WDT) ............................................................................................................................................ 74
10.1 WDT Structure .................................................................................................................................................... 74
10.2 WDT During Idle .................................................................................................................................................. 74
10.3 WDT Register ...................................................................................................................................................... 75
10.4 WDT Hardware Option ........................................................................................................................................ 77
11 Real-Time-Clock (RTC)/System-Timer ..................................................................................................................... 78
12 System Reset ............................................................................................................................................................. 82
12.1 Reset Source ...................................................................................................................................................... 82
12.2 Power-On Reset (POR) ...................................................................................................................................... 82
Note: POF0 must be cleared by software...................................................................................................................... 83
12.3 External Reset ..................................................................................................................................................... 83
12.4 Software Reset .................................................................................................................................................... 84
12.5 Brown-Out Reset ................................................................................................................................................. 84
12.6 WDT Reset.......................................................................................................................................................... 85
12.7 Illegal Address Reset .......................................................................................................................................... 85
13 Power Management ................................................................................................................................................... 86