Crown PSA-2 - Page 94

protection stages of the unit. Also, the output stages can
now be more easily driven from low-voltage stages (ISV)
while operating at +75Vdc, rather than previously higher
voltage requirements for similiar-type circuitry.
As mentioned earlier; because the protection circuitry is
no longer common to the large AC voltage of the output
signal but rather common to ground, a more
sophisticated yet easily monitored circuit is possible. This
complex circuitry is the “heart” of the self-analyzing
amplifier, but is actually easier to trouble-shoot than any
other Crown amplifier.
By using two power transformers rather than one, the
transformer weight is kept close to the rack mounting
surfaces and an additional 40% more power is available.
Another advantage is the independent operation of each
channel, particularly helpful should a supply problem
arise.
A smaller third supply transformer is used for controlling
such features as delay, LF protection, the PSA-2
balanced input module, displays and remote power
control.
Detailed Circuit Theory
The following explanation refers to schematic diagrams
located in the Instruction Manual as well as in Section 6
of this Manual. In most cases, only channel one is
discussed for simplicity.
SA2 Display Module
The display of the SA2 is a combined set of indicators to
show the state of the output signal amplitude, the
dynamic range and to show if the amplifier may be
experiencing any problems.
Amber Power Indicator LED DS, is powered by R6 and
the -24Vdc unregulated supply. Yellow LED’s D100 and
D200 are used to indicate the standby condition of their
respective channels.
As the signal enters the Display Module through pin 14, a
resultant fully rectified signal, one-seventh the amplitude
of the initial input signal, is present at the output of U3B
(U3A, U3B and related circuitry form a full-wave
rectifier).
RII1 and CI01 create an absolute-peak detector,
supplying a smoother dc signal to comparator U6A. The
output of U6A is then determined by the comparison of
the input signal (pin 7) and the log decay oscillator signal
(pin 6) from 500Hz pulse oscillator (USA,B). The lower
the input signal voltage, the shorter the time period
comparator U6A will be turned on (producing +15Vdc
logarithmic pulses). The window (U6B) however,
compares the same tog decay signal (pin 6) to a constant
7-27
: ate i ;
10V on pin 5. When the oscillator signal is greater than
10V, U6B is turned on and produces a +15Vdc at its
output (pin 2). Note here that this output is constant and
is in no way related to the input signal. It is simply used to
limit the upper and lower ends of the pulsating scale.
The output from these comparators then, is fed to
exclusive OR gate USC. The length of time the OR gate is
turned on, is primarily attributed to the pulse transmitted
by the log time base oscillator (USA, B).
The resistors (R114, R115, R116) and capacitors (C102,
C103) following USC are filters that average the overall
DC voltage output. The result is a DC voltage that rises
and falls logarithmically with respect to the input signal.
U2D is a unity gain buffer stage, simply converting a high
impedance signal to a low impedance output . This
output is fed to U2A and associated circuitry,
particularly C104. The level at which C104 charges, is the
level of the peak hold of the display.
C105 is responsible for the actual “hold-time” of the peak
by the amount of time it takes to discharge through R122
and U2B.
The DC voltages from the peak hold circuitry and the
output of the log amp are then multiplexed into one
signal that is fed into the LED display drivers. Here the
signal is divided evenly among 15 LED's. The display will
show one bright illumination shifting with the
“alwayschanging”™ output ‘amplitude while another, less
bright illumination will have a short hold time (about 4
seconds) respective to “peak amplitudes” only. Voltage
divider R126, R127 and R128 assist the display driver in
determining the high and low end of the display scale.
A. Output Stage - PSA-2/SA2
There are two types of output modules within each
amplifier. The module which produces the negative half
of the output current waveform and is powered by the
positive Vcc supply, (this is a result of the inverting
output topology being used), and the module which
produces the positive half of the output waveform and is
powered from the negative Vcc supply. For the sake of
discussion we will call them by the names of the type of
transistor which they simulate (the former being referred
to as the NPN stage and the latter the PNP stage). Note
that this is identical to the type of pre-driver used in each.
The PNP stage is constructed with NPN outputs and
driver, much the same as a Crown DC-300A negative
output stage. The differences are that the current sensing
is the sum of all the collector junctions rather than just
one device. This is necessary to eliminate the TO-3 IC
housing to sink insulating hardware from all of the
devices and maximize the available output power by
keeping the heatsink thermal resistance as low as