Cyrus CD6s - Sheet 2: Clock Generation

22-Mar-2006
O
c
Cyrus Audio Ltd
CD6s Clock generation 2 5ofSheet
PCPout
1
PC1out
2
COMPin
3
VCOout
4
INH
5
C1a
6
C1b
7
GND
8
VCOin
9
DEMout
10
R1
11
R2
12
PC2out
13
SIGin
14
PC3out
15
Vcc
16
IC204
74HC4046
1
2
3
147
IC201A
74HCT86
12
13
11
IC201D
74HCT86
4
5
6
IC201B
74HCT86
9
10
8
IC201C
74HCT86
DGND
PHASE
I2S_DATA
I2S_WCLK
I2S_SCLK
PHASE data inversion 0 normal 1 Inverted
+5VCD
RP201
100R * 4
D0
2
Q0
19
D1
3
Q1
18
D2
4
Q2
17
D3
5
Q3
16
D4
6
Q4
15
D5
7
Q5
14
D6
8
Q6
13
D7
9
Q7
12
OE
1
CP
11
GND
10
VCC
20
IC202
74HC574
RP202100R * 4
RP203
100R * 4
RP204
100k * 4
RP205
100k * 4
DAC_WCLK
DAC_LDATA
DAC_RDATA
DAC_BCLK
IEC958_WCLK
IEC958_DATA
IEC958_BCLK
DGND
XCLK/8 XCLK
P3
6
P2
5
P1
4
P0
3
PE
9
CEP
7
CET
10
CP
2
TC
15
MR
1
Q0
14
Q1
13
Q2
12
Q3
11
VCC
16
GND
8
IC205
74HC161
+5VCD
C205
10n 0603
DGND
DGND
XCLK/8
XCLK=16.9344MHz(384fs)
XCLK/8=2.1168MHz(48fs)
L201
1uH
R209
47R
R210
91R
C209
100uF/16V
DGND
C206
10n 0603
R204
150R 0603
R212
0R
R203
47k
DGND
+5VCC_PLL
DGND
C210
22uF/16V
C207
10n 0603
C208
68pF
R208
3k3
DGND
XCLK
DAC_INHIBIT
R201
47k
+5VCD
+5VCD
+5VCD
C201
10n 0603
DGND
C202
470n 0603
DGND
1 2
147
IC203A
74HC14
3 4
IC203B
74HC14
+5VCD
C203
470nF 16V 0603
DGND
DGND
DAC_XCLK
R213
100R 0603
R215
150R 0603
BCLK
DGND
R218
100R 0603
DATA: Left Justified
BCLK: 48fs
WCLK: L- /R
XCLK: 384fs
Wima FKP2
R219
150R 0603
R220
100R 0603
CLK
3
PRE
4
CLR
1
D
2
Q
5
Q
6
VDD
14
IC206A
74HC74
CLK
11
PRE
10
CLR
13
D
12
Q
9
Q
8
GND
7
IC206B
74HC74
R217
100R 0603
R216
100R 0603
+5VCD
C211
10n 0603
DGND DGND
/BCLKBCLK
/WCLK LEFTJUST_WCLK
+5VCD +5VCD
+5VCD
XCLK
WCLK
/WCLKWCLK
LEFTJUST_WCLK
R221
100R 0603
Cyrus CD6s Service Manual Issue 1