Datalogic DLR-TL001 - Two Main Register Descriptions

DLR-TL001 Memory Description
12 DLR-TL001
Two Main Register Descriptions
The user can get a detailed description of the Registers In
the Product Reference Guide and in the Programming
Manual.
Here below, only the CONTROL and STATUS Registers will
be described at Bit/ Flag level to improve the reading of
this quick guide.
The CONTROL Register’s 16 bits are the following:
0 - RST (RW) - Reset bit: used to erase all the log memory
and reset all the memory pointers and counters included
the histogram bins.
1 - BE (RW) - Button_Enable bit: if 1, the DLR-TL001 but-
ton can be used to start and to stop the logging activity.
2 - LE (RW) - Logging_Enable bit: if 1, the logging activity is
enabled.
3 -DE (RW) - Delay_Enable bit: If 1, the first sample's
acquisition is given a preset number of seconds after log-
ging starts.
4 - RFSL (RW) - RF_Sensitivity_Level: used to set the sen-
sitivity level of radio freq. front-end. 3 levels: 3 = max, 1 =
min. Default value 1.
5 - MKTE (RW) - Mean_Kinetic_Enable bit: if 1, the MKT
calculation is enabled. Default value is 0.
6 - ARRE (RW) - Arrhenius_Enable bit: if 1, the calculation
of the remaining Shelf Life is enabled. Default value is 0.
11 - SD (RW) - Stop_Disable bit: if 1, the DLR-TL001 button
cannot be used to stop the logging activity. Default value
is 0.
8 to 10 & 12 to 15 Bits are RFU (RW) bits (Reserved for
Future Use).